ADAR1000ACCZN-R7 datasheet(40/79 Pages) AD

40 / 79 page

Data Sheet

ADAR1000

APPLICATIONS INFORMATION

analog.com

Rev. B | 40 of 79

LNA BIAS OUTPUT CONTROL

The LNA_BIAS output voltage is controlled by a DAC, which in turn

is controlled by a combination of inputs (see Table 17).

The output is set by the LNA_BIAS_ON data when the ADAR1000

is in receive mode or LNA_BIAS_OFF data when in transmit mode,

if BIAS_CTRL is set to 1. If BIAS_CTRL set to 0, the output is set

by LNA_BIAS_ON data. See Table 18 for all control combinations.

Table 17. LNA Bias Output Control by Inputs

Input

Bit/Pin Name

Description

Bit 4

LNA_BIAS_OUT_EN

The LNA_BIAS output is enabled if LNA_BIAS_OUT_EN = 1. If LNA_BIAS_OUT_EN = 0, the output is

open (three-state).

Bit 6

BIAS_CTRL

Determines if the bias DAC always use the EXT_LNA_BIAS ON data (BIAS_CTRL = 0) or if the bias DAC

can be controlled with the other inputs (BIAS_CTRL = 1).

Bit 2

TR_SOURCE

Determines whether switching between transmit and receive mode is controlled by the SPI register or the

TR input.

Bit 6

RX_EN

Global receive enable. Logic high enables all four receive paths (if individual Chx_RX_EN bits are also

logic high). See Figure 93.

tions in memory; see the memory map

on the ADAR1000 product page.

EXT_LNA_BIAS_ON

External LNA Bias on data that can be sourced from multiple locations.

tions in memory; see the memory map

on the ADAR1000 product page.

EXT_LNA_BIAS_OFF

External LNA Bias off data that can be sourced from multiple locations.

Input Pin

Determines transmit or receive mode of chip when TR_SOURCE = 1

Table 18. Control of LNA_BIAS Output

LNA_BIAS_OUT_EN

(Register 0x030, Bit 4)

BIAS_CTRL

(Register 0x030, Bit 6)

TR_SOURCE

(Register 0x031, Bit 2)

RX_EN

(Register 0x031, Bit 5)

(Input to Chip)

LNA Bias Bits Used

Open circuit (floating)

EXT_LNA_BIAS_ON

EXT_LNA_BIAS_OFF

EXT_LNA_BIAS_ON

EXT_LNA_BIAS_OFF

1 X means don't care.

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