| Electronic Components Datasheet Search |
|
ADAR1000ACCZN-R7 Datasheet(PDF) 8 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
ADAR1000ACCZN-R7 Datasheet(HTML) 8 Page - Analog Devices |
|
8 / 79 page ![]() Data Sheet ADAR1000 SPECIFICATIONS analog.com Rev. B | 8 of 79 Table 1. Parameter Test Conditions/Comments Min Typ Max Unit Voltage Range −4.8 to 0 V Source and Sink Current −10 to+10 mA Off to On Switching Time From TR or CSB at 50% to VOUT at 90%, VOUT from −2 V to −1 V, 1 nF CLOAD 60 ns On to Off Switching Time From TR or CSB at 50% to VOUT at 10%, VOUT from −1 V to −2 V, 1 nF CLOAD 60 ns TRANSMIT AND RECEIVE MODULE CONTROL TR_SW_POS, TR_SW_NEG, TR_POL pins Voltage Range TR_SW_NEG, TR_POL −4.8 to 0 V TR_SW_POS 0 to 3.2 V Off to On Switching Time From TR or CSB at 50% to VOUT at 90% 15 ns On to Off Switching Time From TR or CSB at 50% to VOUT at 10% 15 ns LOGIC INPUTS7 TR, RX_LOAD, TX_LOAD, CSB, SCLK, and SDIO pins Input High Voltage (VIH) 1.0 V Input Low Voltage (VIL) 0.4 V High and Low Input Current (IINH, IINL) ±1 µA Input Capacitance (CIN) 1 pF LOGIC OUTPUTS SDO and SDIO pins Output High Voltage (VOH) Output high current (IOH) = 0 mA (open circuit) 1.8 V Output Low Voltage (VOL) Output low current (IOL) = 0 mA (open circuit) 0 V Output High Voltage (VOH) Output high current (IOH) = −10 mA 1.4 V Output Low Voltage (VOL) Output low current (IOL) = 10 mA 0.4 V POWER SUPPLIES AVDD1 −5.25 −5 −4.75 V AVDD3 3.1 3.3 3.5 V IAVDD1 Quiescent (reset state) −4 mA IAVDD1 PA bias outputs fully loaded −50 mA IAVDD3 Reset Mode (Standby) 23 mA Transmit Mode Four channels enabled, nominal bias 350 mA Four channels enabled, low bias setting 240 mA Receive Mode Four channels enabled, nominal bias 260 mA Four channels enabled, low bias setting 160 mA 1 Single channel transmit gain defined as the ratio of output power at any Tx output port to the input power applied to the RF_IO port. 2 From one transmit channel port to another, both channels must be set to the maximum gain. 3 Single channel receive gain is the ratio of the output power at RF_IO to the input power applied to any single receive port, with the other three receive ports terminated in 50 Ω. 4 Electronic gain is the ratio of the output power at RF_IO to the input power applied to any single receive port, with the other three receive ports driven and phased for coherent combining with 6 dB subtracted. The electronic gain is approximately 6 dB higher than the single path gain, and 6 dB lower than coherent gain. 5 Coherent gain is the ratio of output power at RF_IO to the input power applied to any single receive port, with the other three receive ports driven and phased for coherent combining. 6 From one receive channel port to another, both channels must be set to the maximum gain. 7 Inputs have 100 mV (typical) of hysteresis. TIMING SPECIFICATIONS AVDD1 = −5 V, AVDD3 = +3.3 V, TA = 25°C, unless otherwise noted. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |