ST10F272M datasheet(29/175 Pages) STMICROELECTRONICS

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ST10F272M

Internal Flash memory

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5.4.2

Flash control register 0 high (FCR0H)

The Flash Control Register 0 High (FCR0H) together with the Flash Control Register 0 Low

(FCR0L) is used to enable and to monitor all the write operations on the IFlash. The user

has no access in write mode to the Test-Flash (B0TF). Moreover, the Test-Flash block is

seen by the user in Bootstrap mode only.

Table 7.

Flash control register 0 low

Bit Name

Function

4LOCK

Flash Registers Access Locked

When this bit is set, it means that the access to the Flash Control Registers FCR0H/-

FCR1H/L, FDR0H/L-FDR1H/L, FARH/L and FER is locked by the FPEC: any read

access to the registers will output invalid data (software trap 009Bh) and any write

access will be ineffective. LOCK bit is automatically set when the Flash bit WMS is set.

This is the only bit the user can always access to detect the status of the Flash: once it is

found low, the rest of FCR0L and all the other Flash registers are accessible by the user

as well.

Note that FER content can be read when LOCK is low, but its content is updated only

when the BSY0 bit is reset.

1BSY0

Bank 0 Busy (IFlash)

This bit indicates that a write operation is running on Bank 0 (IFlash). It is automatically

set when bit WMS is set. Setting Protection operation sets bit BSY0 (since protection

registers are in this Block). When this bit is set, every read access to Bank 0 will output

invalid data (software trap 009Bh), while every write access to the Bank will be ignored.

At the end of the write operation or during a Program or Erase Suspend this bit is

automatically reset and the Bank returns to read mode. After a Program or Erase

Resume this bit is automatically set again.

FCR0H (0x08 0002)

FCR

Reset value: 0000h

987

65432

WMS

SUSP

WPG DWPG

SER

Reserved

SPR

Reserved

Table 8.

Flash control register 0 high

Bit Name

Function

WMS

Write Mode Start

This bit must be set to start every write operation in the Flash module. At the end of the

write operation or during a Suspend, this bit is automatically reset. To resume a

suspended operation, this bit must be set again. It is forbidden to set this bit if bit ERR of

FER is high (the operation is not accepted). It is also forbidden to start a new write

(program or erase) operation (by setting WMS high) when bit SUSP of FCR0 is high.

Resetting this bit by software has no effect.

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