Broadcom

ACPL-C877-DS100

8

ACPL-C877 Data Sheet

Precision Optically Isolated Digital Voltage Sensor

Timing Specifications

Unless otherwise noted, TA = –40°C to +110°C, VDD1 = 4.5V to 5.5V, VDD2 = 3V to 5.5V.

Power Supply

VDD1 Supply Current

IDD1

—8

13

mA

VIN+ = 0V to 2V.

10

VDD2 Supply Current

IDD2

—6.8

10

mA

11

—6.0

8.5

mA

VDD2 = 3.3V supply.

12

a. All Typical values are at TA = 25°C, VDD1 = 5V, VDD2 = 5V.

b. Gain Error Drift vs. VDD1 is expressed as 5 mV/V with reference to VREF.

c. Beyond the full-scale input range, the data output is either all zeros or all ones.

Parameter

Symbol

Min.

Typ.

Max.

Units

Test Conditions

Notes Figure

Modulator Clock Output Frequency

fMCLK

910

11

MHz CL = 15 pF

a

a. fMCLK specification is based on average value which is equal to SDM CLK.

13

Modulator Clock Rising Time

tr

—5—

ns

CL = 15 pF

Modulator Clock Falling Time

tf

—5—

ns

CL = 15 pF

Data Setup Time after MCLK Rising Edge

tS

50

—

—

ns

CL = 15 pF

4

Data Hold Time after MCLK Rising Edge

tH

10

—

—

ns

CL = 15 pF

4

Clock and Data Startup Time

tSTART

—0.5

—

ms

VDD1 step to 4.5V, VDD2 >3.0V.

5

Parameter

Symbol

Min.

Typ.a

Max.

Units

Test Conditions

Figure

Figure 4: Data Timing

Figure 5: Clock and Data Startup Time