© 2021 Renesas Electronics Corporation

3

Sep 28, 2021

F1951 SPECIFICATION (31.5 dB Range)

Specifications apply at VDD = +3.3V, fRF = 2000MHz, TC= +25°C unless otherwise noted, EVKit losses are de-embedded (see p. 17)

Parameter

Comment

Sym.

Min

Typical

Max

Units

Logic Input High

CLK, CSb, DATA, D[5:0],

RSTb

VIH

2.3[a]

3.6[b]

V

Logic Input Low

CLK, CSb, DATA, D[5:0],

RSTb

VIL

0.7

V

Logic Current

VMODE

IIH, IIL

-5

+5

µA

Supply Voltage(s)

Main Supply

VDD

3.0

5.25

V

Supply Current

Total

IDD

1.1

2

mA

Temperature Range

Operating Range (Case)

TC

-40

100

°C

Frequency Range

Operating Range

fRF

100

5000

MHz

RF1, RF2 Return Loss

dB(s11), dB(s22)

S11, S22

-22

dB

Minimum Attenuation

D[5:0] = [111111]

AMIN or IL

1.2

1.9

dB

Maximum Attenuation

• D[5:0] = [000000]

• VDD = 3.3V

AMAX

32.2

32.5

dB

Minimum Gain Step

Least Significant Bit

LSB

0.50

dB

Phase Delta

Phase change AMIN vs. AMAX

ΦΔ

33

deg

Differential Non-Linearity

Error: adjacent steps

DNL

0.08

dB

Integral Non-Linearity

Error: absolute to 14 dB

ATTN

INL1

0.03

0.34

dB

Integral Non-Linearity

Max Error vs. line (AMIN ref)

to 31.5 dB ATTN [VDD =

3.3V]

INL2

0.21

0.38

dB

Input IP3

 PIN = +10 dBm per tone

 50 MHz Tone Separation

 VDD = 3.3V

dBm

D[5:0] = [111111] = AMIN

IP3I1

+61

+64

D[5:0] = [100000] = A15.5

IP3I2

+59

+61

D[5:0] = [000000] = AMAX

IP3I3

+57

+61

0.1 dB Compression

Please note ABS

MAX

 D[5:0] = [111010] = A2.5

 Baseline PIN = 20 dBm

P0.1

29

dBm

Settling Time

 Start LE rising edge > VIH

 End +/-0.10 dB Pout

settling

 15.5 – 16.0 transition

TLSB

400

ns

Serial Clock Speed

SPI 4 wire bus

FCLK

20

50

MHz

Reset to Serial Setup

SPI 4 wire bus

A

20

ns

Serial Data Hold Time

SPI 4 wire bus

B

5

ns

CSb setup delay

SPI 4 wire bus

C

40

ns

Serial Data Out Delay

SPI 4 wire bus

D

8

8

8

Cycles

[a] – Items in min/max columns in bold italics are Guaranteed by Test.

[b] – All other Items in min/max columns are Guaranteed by Design Characterization.