© 2021 Renesas Electronics Corporation

4

Sep 28, 2021

SERIAL CONTROL MODE

Data is clocked in LSB first via serial mode. Note the timing diagram below.

An RSTb pulse resets the shift register to [00000000]. If the RSTb pulse is followed immediately by a CSb pulse the

device will be set to Maximum Attenuation.

Note – The F1951 includes a CLK inhibit feature designed to minimize sensitivity to CLK bus noise when the device

is not being programmed. When CSb is high (> VIH), the CLK input is disabled and serial data (SDI) will not be clocked

into the shift register. It is recommended that CSb be pulled high (>VIH) when the device is not being programmed

SERIAL REGISTER TIMING DIAGRAM [SINGLE DEVICE]: (Note the Timing Spec Intervals in Blue)

X

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

X

0.5 dB

1 dB

2 dB

4 dB

8 dB 16 dB

R0

R1

D0

D1

D2

D3

D4

D5

RSV

MSB

Data Word IN 8 bits

RSTb

CLK

CSb

SDI

SDO

Serial Input Data

read into shift register

on rising edge of CLK

Data Word latched into

active register on rising

edge of CSb

C

C

B

A

RSV

While CSb is low, SDO transmits the

contents of the shift register delayed by 8

clock cycles

When CSb is high, SDO is quiet

Time