© 2021 Renesas Electronics Corporation

5

Sep 28, 2021

SERIAL REGISTER TIMING DIAGRAM [TWO OR MORE DEVICES]:

The SDO output is delayed by 8 clock cycles while CSb is low. The SDO low logic voltage is 0 volts and the SDO high

logic voltage is VDD/2. This feature allows one to program multiple DSAs (in a MIMO transceiver for instance) with a

single common CSb line by daisy-chaining the SDO of the 2nd DSA to the SDI of the 1st DSA and so forth:

X

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

X

0.5 dB

1 dB

2 dB

4 dB

8 dB 16 dB

R0

R1

D0

D1

D2

D3

D4

D5

RSV

MSB

Word1 8 bits

C

C

B

RSV

SDO returns the 1

st word written which will program DSA1

On CSb rising edge

Word2 programs

DSA2 and Word1

programs DSA1

X

X

0.5 dB

1 dB

2 dB

4 dB

8 dB 16 dB

R0

R1

D0

D1

D2

D3

D4

D5

Word2 8 bits

X

X

0.5 dB

1 dB

2 dB

4 dB

8 dB 16 dB

R0

R1

D0

D1

D2

D3

D4

D5

Word1 8 bits

SDO Quiet

SDO Quiet

D

CSb

SDI

SDO

CLK

DSA2

CSb

SDI

SDO

CLK

DSA1

Chip Select

Data

Clock

SPI

Controller

MSB

CLK

CSb

SDI

SDO

SERIAL REGISTER DEFAULT CONDITION [F1951]:

When the device is first powered up, it will default to the Maximum Attenuation setting as described below:

Note that for the F1951 (High or 1) = Attenuation Stepped OUT. (0 or Low) = Attenuation Stepped IN.

SERIAL REGISTER TIMING TABLE [F1951]:

Interval

Symbol

Description

Min

Spec

Max

Spec

Units

A

Reset to Serial Setup Time

20

ns

B

Serial Data Hold Time

5

ns

C

CSb setup delay

40

ns

D

Serial Data Out Delay

8

8

Cycles

Default Register Settings

0

0

0

0

0

0

0

0

R0

R1

D3

D0

D2

D1

LSB

D5

MSB

D4

RSV

RSV