AMC7820YSLASH2K datasheet(14/29 Pages) TI2

14 / 29 page

AMC7820

SBAS231B

www.ti.com

OVERVIEW

The AMC7820 is an analog monitoring and control circuit for

control of laser diodes and TEC coolers in DWDM applica-

tions. A register-based architecture eases integration with

DSP-based (or microprocessor-based) systems through a

standard SPI bus. All peripheral functions are controlled

through the registers and onboard state machines.

The AMC7820 consists of the following blocks (refer to the

block diagram of Figure 2):

• 8-Channel, 12-Bit ADC

• Three 12-Bit DACs

• Nine Operational Amplifiers

• +2.5V Reference

• TEC Soft Start Controller

Communication to the AMC7820 is via a standard SPI serial

interface. This interface requires that SS, the Slave Select

signal, be driven LOW to communicate with the AMC7820.

The data is then shifted into and out of the AMC7820 under

control of the host DSP or microprocessor, which also

provides the serial data clock.

Control of the AMC7820 and its functions is accomplished by

writing to different registers in the AMC7820. A simple com-

mand protocol is used to address the 16-bit registers. Regis-

ters control the operation of the ADC, DACs, and device

configuration. The results of measurements made are placed

in the memory map and can be read by the host at any time.

All pins have ESD protection circuitry as the first active

element on the chip. All input and output pins have protection

diodes connected to supply and ground that remain reverse

biased under normal operation. If the input voltages exceed

the absolute maximum voltage range, it is necessary to add

resistance in series with the input to limit the current to 10mA

or less.

ADC

The analog inputs are provided via a multiplexer to the

Successive Approximation Register (SAR) ADC. The ADC

architecture is based on capacitive redistribution architecture

that inherently includes a sample-and-hold function.

The multiplexer provides eight analog input channels to the

ADC. Channels 0, 1, 6, and 7 are buffered by amplifiers

OPA3, OPA4, OPA5, and OPA6, respectively. Channels 2,

3, 4, and 5 connect directly to external pins. The multiplexer

connects each analog input to the ADC sequentially. Analog

current into the device must charge the internal sample-

and-hold capacitor during the sampling period. When the

converter is in Hold mode, and the sampling capacitor has

been fully charged, the input impedance of the analog input

is greater than 1G

Ω.

The on resistance of each multiplexer switch is typically

150

Ω. In order to charge the internal sample-and-hold ca-

pacitor completely during the acquisition time, the source

impedance of the analog input should be no more than 1k

Ω.

The ADC runs continuously upon start-up, scanning through

each channel. The results of conversions made are stored in

the appropriate ADC registers.

Since the input range of the ADC is 2 • VREF, codes near FFF

will be missing if the output range of the signal source driving

an ADC input channel is limited to less than 2 • VREF. This is

the case for channels 0, 1, 6, and 7 which are driven from

internal op amps which have an output range limit of AVDD.

If all codes including FFF are required, the value of the

reference voltage must be reduced or the value of AVDD must

be increased.

Data Format

The AMC7820 output data is in Straight Binary format, as

shown in Figure 1. This figure shows the ideal output code for

the given input voltage and does not include the effects of

offset, gain, or noise.

DACS

The three 12-bit DACs of the AMC7820 use a resistor-string

architecture with switchable taps that are buffered by an

operational amplifier (see DAC0 in Figure 4). Each op amp

buffer can be configured for a gain of +1 or +2, which sets the

output range to 0V to +2.5V or 0V to +5.0V, respectively. This

architecture is inherently monotonic, a critical requirement for

any system requiring “smooth” setpoint control.

The op amp buffer has a rail-to-rail output stage that has

limitations on sinking or sourcing current when the output

voltage is near AGND or AVDD, respectively (see the typical

characteristics). For example, if a DAC (Gain = +1) is set to

code 010H (+10mV) and is required to sink 1mA of current,

the DAC output voltage will be approximately 250mV instead

of the desired value of +10mV.

This problem is solved by restricting the DAC output voltage

to values greater than +250mV or by reducing the required

sink current. This restriction does not apply for the case of

sourcing current for gain set at +1. When the gain is set at +2,

there is a limitation on sourcing current with the output

voltage near the positive supply rail.

The slope of the DAC output voltage curve for sinking or

sourcing current is due to an increase in the inherent closed-

loop output impedance of the operational amplifier buffer, when

operating near a supply rail. Refer to the typical characteristic

curves.

FIGURE 1. Ideal Input Voltage and Output Codes.

FS = Full-Scale Voltage = 2V

REF

1LSB = 2V

REF/4096

FS – 1LSB

11...111

11...110

11...101

00...010

00...001

00...000

1LSB

Input Voltage (V)

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