AMC7820

SBAS231B

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25

SW1/SW2

SW1/SW2

1

0

OPERATION

0

0

Invalid—a write of this value will not result in any change to the bit values stored in the register.

0

1

Enable (the normal operating mode). SW1 connects to DAC2, and SW2 connects to the output of OPA7.

1

0

Disable (condition after power-up or reset). SW1 connects to ground, and SW2 connects to SW3.

1

1

Invalid—a write of this value will not result in any change to the bit values stored in the register.

TABLE V. Shutdown Bit Patterns.

The default state of this register upon power-up or reset is such that both SW1 and SW2 are disabled (0x000A). The logic level

of signal SW1_DISABLE is HIGH when switch SW1 is disabled, and LOW when SW1 is enabled. The logic level of signal

SW2_DISABLE is HIGH when switch SW2 is disabled, and LOW when SW2 is enabled.

AMC7820 RESET REGISTER

The AMC7820 has a special register, the RESET register, which acts like the RESET pin of the device. Writing the code

0xXBB3, as shown below, to this register will cause the AMC7820 to perform a software reset. Note that only the lower 12 bits

have significance for this reset function.

POL1

POL0

OPERATION

0

0

Invalid—a write of this value will not result in any change to the bit values stored in the register.

0

1

Bipolar Mode. SW3 is positioned to 2.5V. (Condition after power-up or reset.)

1

0

Unipolar Mode. SW3 is positioned to AGND.

1

1

Invalid—a write of this value will not result in any change to the bit values stored in the register.

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MSB

LSB

X

X

X

X

1

01

11

011

0

0

1

1

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MSB

LSB

X

X

X

X

X

X

X

X

X

X

X

RSTC

POL1

POL0

TS1

TS0

TS1

TS0

OPERATION

0

0

SOFT_START_CTR is LOW (“0”). TEC SOFT_START_CONTROLLER is disabled regardless of the status of SW2.

0

1

SOFT_START_CTR is HIGH (“1”). TEC SOFT_START_CONTROLLER is enabled if SW2 is disabled (SW2_DISABLE = HIGH (“1”))

(Condition after power-up or reset.)

1

0

SOFT_START_CTR is LOW (“0”). TEC SOFT_START_CONTROLLER is disabled regardless of the status of SW2.

1

1

Invalid—a write of this value will not result in any change to the status of SOFT_START_CTR.

where,

x = Don’t Care.

Writing any other values to this register will do nothing. Upon reset, this register is set to all zeros. Therefore, reading this register

should always result in reading back 0x0000.

AMC7820 CONFIGURATION/STATUS REGISTER

AMC7820 can be configured to control bidirectional TEC and single direction TEC by properly setting SW3 and

TEC_SOFT_START_CONTROLLER. This is accomplished by writing a proper word into this register.

A reset status bit indicates if a reset has occurred. The register is formatted as follows:

TABLE VI. Polarity Bit Operation.

TABLE VII. TEC Soft Start Enable Bit Operation.

where,

RSTC—Reset Complete. This bit is set to “1” on power-up or reset. This bit can be cleared by writing a “0” to this location, but

it cannot be set to “1” by the host, only a reset being performed will set it to 1. This allows the host to determine if the part has

been configured after power-up, and if a reset has occurred to the AMC7820 without the host’s knowledge.

POL0 – POL1—Polarity bits that control SW3. The operation is shown in Table VI. After power-up or reset, these bits are set

to bipolar mode, and SW3 is positioned to 2.5V.

TS1 – TS0—TEC Soft Start Enable Bits, which determine the status of the signal SOFT_START_CTR. The operation is shown

in Table VII. After power-up or reset, TS1 = “0”, TS0 = “1”, SOFT_START_CTR = HIGH (“1”).