CC1050-RTR1 datasheet(13/43 Pages) TI2

13 / 43 page

CC1050

SWRS044

Page 13 of 40

Figure 5. Configuration registers read operation

Parameter

Symbol

Min

Max

Units

Conditions

PCLK, clock

frequency

FCLOCK

MHz

PCLK low

pulse

duration

TCL,min

The minimum time PCLK must be low.

PCLK high

pulse

duration

TCH,min

The minimum time PCLK must be high.

PALE setup

time

TSA

The minimum time PALE must be low before

negative edge of PCLK.

PALE hold

time

THA

The minimum time PALE must be held low after

the positive edge of PCLK.

PDATA setup

time

TSD

The minimum time data on PDATA must be ready

before the negative edge of PCLK.

PDATA hold

time

THD

The minimum time data must be held at PDATA,

after the negative edge of PCLK.

Rise time

Trise

100

The maximum rise time for PCLK and PALE

Fall time

Tfall

100

The maximum fall time for PCLK and PALE

Note: The set-up- and hold-times refer to 50% of VDD.

Table 2. Serial interface, timing specification

PCLK

Address

Read mode

Data byte

PALE

PDATA

Not Recommended for New Designs

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