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LM10504

SNVS739F – DECEMBER 2011 – REVISED OCTOBER 2016

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Device Functional Modes (continued)

7.4.4 DevSLP Function

The device can be placed into sleep (DevSLP) mode. There are two ways for doing that:

1. DevSLP pin

2. Programming through the SPI

Bucks 1 and 2 are ramped down when the disable signal is given. Buck 1 starts ramping 2 ms after Buck 2 has

started ramping.

To enter the DevSLP sequence:

1. Buck 3

→ PSML (Programmable DevSLP Mode Level)

2. 2-ms delay

3. Buck 2

→ Disabled

4. 2-ms delay

5. Buck 1

→ Disabled

7.4.4.1 DevSLP Pin

When the DevSLP pin is asserted high, the LM10504 enters sleep mode. While in sleep mode, Buck 1 and Buck

2 are disabled. Buck 3’s output voltage is transitioned to the programmable sleep mode level (PSML) as set by

LM10504 register 0x09. The DevSLP pin is internally pulled down, and there is a 1-s delay during power up

before the state of the DevSLP pin is checked.

NOTE

If Buck 1 and Buck 2 are already disabled, and the DevSLP pin is asserted high, then

Buck 3 does not go to PSML. For further instructions, see DevSLP Programming Through

SPI. Bucks 1 and 2 are ramped down when the disable signal is given. Buck 1 starts

ramping 2 ms after Buck 2 has started ramping.

To enter the sleep sequence:

1. Buck 3

→ PSML

2. 2-ms delay

3. Buck 2

→ Disabled

4. 2-ms delay

5. Buck 1

→ Disabled

An internal 22-kΩ pulldown resistor (±30%) is attached to the FB pin of Buck 1 and Buck 2. Buck 1 and 2 outputs

are pulled to ground level when they are disabled to discharge any residual charge present in the output circuitry.

When Sleep transitions to a low, Buck 1 is again enabled followed by Buck 2. Buck 3 goes back to its previous

state.

When waking up from sleep mode, the sequence is:

1. Buck 1

→ Previous state

2. 2-ms delay

3. Buck 2 and Buck 3 transition together

→ Previous state

7.4.4.2 DevSLP Programming Through SPI

There is no bit which has the same function as DevSLP pin. There is only one requirement programming

LM10504 into DevSLP mode through SPI. Setting LDO sleep mode bit high must be the last move when entering

DevSLP mode and programming the bit low when waking from DevSLP mode must be the first move. Disabling

or programming the Bucks to new level is the user’s decision based on power consumption and other

requirements.