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LM10504

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SNVS739F – DECEMBER 2011 – REVISED OCTOBER 2016

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Copyright © 2011–2016, Texas Instruments Incorporated

Device Functional Modes (continued)

The following section describes how to program the chip into sleep mode corresponding to DevSLP pin function.

To program the LM10504 to sleep mode through SPI, Buck 1 and Buck 2 must be disabled by host device

(Register 0x0A bit 1 and 0). Buck 3 must be programmed to desired level using Register 0x00. After Buck 3 has

finished ramping, LDO sleep mode bit must be set high (Register 0x0E bit 1). To wake LM10504 from sleep

mode, LDO sleep mode bit must be set low (Register 0x0E bit 1). Buck 1 and 2 must be enabled. Buck 3 voltage

must be programmed to previous output level.

7.4.4.3 DevSLP Operational Constraints

In sleep mode the device is in a low power mode. All internal clocks are turned off to conserve power and Buck 3

only operates in PFM mode. While limited to PFM mode the loading on Buck 3 must be kept below 80 mA

(typical) to remain below the PFM/PWM threshold and avoid device shutdown. The device loading must be

lowered accordingly before entering sleep mode through DevSLP.

7.4.5 Vselect_B2, Vselect_B3 Function

The Vselect_B2/3 pins are digital pins which control alternate voltage selections of Buck 2 and Buck 3,

respectively. Vselect_B2 has an internal pulldown which defaults to a 1.8-V output voltage selection for Buck 2.

Alternatively, if Vselect_B2 is driven high, an output voltage of 3 V is selected. Vselect_B3 has an internal pullup

which defaults to a 1.2-V output voltage selection for Buck 3. Alternatively, if Vselect_B3 is driven low, an output

voltage of 1 V is selected. The pullup resistor is connected to the main input voltage. Transitions of the pins does

not affect the output voltage, the state is only checked during start-up.

7.4.6 Undervoltage Lockout (UVLO)

The VIN voltage is monitored for a supply under voltage condition, for which the operation of the device can not

be ensured. The part automatically disables Buck 3. To prevent unstable operation, the undervoltage lockout

(UVLO) has a hysteresis window of about 300 mV. An UVLO forces the device into the reset state, all internal

registers are reset. Once the supply voltage is above the UVLO hysteresis, the device initiates a power-up

sequence and then enter the active state.

Buck 1 and Buck 2 remain in bypass mode after VIN passes the UVLO until VIN reaches approximately 1.9 V.

When Buck 2 is set to 1.8 V, the voltage jumps from 1.8 V to VUVLO_FALLING, and then follow VIN.

The LDO and the comparator remains functional past the UVLO threshold until VIN reaches approximately

2.25 V.

7.4.7 Overvoltage Lockout (OVLO)

The VIN voltage is monitored for a supply overvoltage condition, for which the operation of the device cannot be

ensured. The purpose of overvoltage lockout (OVLO) is to protect the part and all other consumers connected to

the PMU outputs from any damage and malfunction. Once VIN rises over 5.64 V all the Bucks, and LDO is

disabled automatically. To prevent unstable operation, the OVLO has a hysteresis window of about 100 mV. An

OVLO forces the device into the reset state; all internal registers are reset. Once the supply voltage is below the

OVLO hysteresis, the device initiates a power-up sequence, and then enter the active state. Operating maximum

input voltage at which parameters are ensured is 5.5 V. Absolute maximum of the device is 6 V.

7.4.8 Device Status, Interrupt Enable

The LM10504 has 2 interrupt registers, INTERRUPT ENABLE and INTERRUPT STATUS. These registers can

be read through the serial interface. The interrupts are not latched to the register, always represents the current

state, and does not clear on read.

If interrupt condition is detected, then corresponding bit in the INTERRUPT STATUS register (0x0D) is set to '1',

and Interrupt output is asserted. There are 5 interrupt generating conditions:

•

Buck 3 output is over flag level (90% when rising, 85% when falling)

•

Buck 2 output is over flag level (90% when rising, 85% when falling)

•

Buck 1 output is over flag level (90% when rising, 85% when falling)

•

LDO is over flag level (90% when rising, 85% when falling

•

Comparator input voltage crosses over selected threshold