START

MSB

DEVICE ADDRESS

LSB

ACK

SCL

SDA

STOP

MSB

REGISTER DATA

LSB

ACK

R/W

LM48557

SNAS486D – JULY 2009 – REVISED MAY 2013

www.ti.com

Figure 19. Example Write Sequence

Table 2. Device Address

B7

B6

B5

B4

B3

B2

B1

B0 R/W

Device Address

1

1

0

1

1

1

1

0

Table 3. Control Registers

Register

B7

B6

B5

B4

B3

B2

B1

B0

Name

Mode Control

0

0

0

0

0

0

MUTE

SHDN

Volume Control

1

0

VOL5

VOL4

VOL3

VOL2

VOL1

VOL0

Table 4. Mode Control Registers

BIT

NAME

VALUE

DESCRIPTION

DEFAULT SETTING

0

Shutdown mode

B0

SHDN

0

1

Normal operation

0

Normal operation

B1

MUTE

0

1

Device mute, AV = -90dB.

B2

RESERVED(1)

X

Unused, Set to 0

0

B3

RESERVED(1)

X

Unused, Set to 0

0

B4

TESTMODE

0

Set B4 to 0. B4 = 1 enables TESTMODE. See TEST MODE.

0

B5

RESERVED(1)

X

Unused, Set to 0

0

B6

RESERVED(1)

X

Unused, Set to 0

0

REGISTER

B7

0

Set to 0 to access Mode Control register

0

ADDRESS

(1)

RESERVED bits are Don't Cares and are ignored by the device. The state of the RESERVED bits does not affect device operation.

Table 5. Volume Control Registers

BIT

NAME

VALUE

DESCRIPTION

DEFAULT SETTING

B0:B5

VOL0:VOL5

See Table 6

Controls amplifier gain/attenuation

0

B6

RESERVED(1)

X

Unused, Set to 0

0

REGISTER

B7

1

Set to 1 to access Volume Control register

1

ADDRESS

(1)

RESERVED bits are Don't Cares and are ignored by the device. The state of the RESERVED bits does not affect device operation.

SINGLE AND MULTI-BYTE WRITE OPERATION

The LM48557 supports both single-byte and multi-byte write operations. A single-byte write operation begins with

the master device transmitting a START condition followed by the device address (Figure 20). After receiving the

correct device address, the LM48557 generates an ACK bit. The master device transmits the register data byte,

after which the LM48557 generates and ACK bit. Following the ACK, the master issues a STOP condition,

completing the singly-byte data transfer.

10

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