PCM1738ESLASH2K.B datasheet(29/47 Pages) TI2

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PCM1738

SBAS174C – FEBRUARY 2002 – REVISED FEBRUARY 2007

CHSL

Channel Selection for Monaural Mode

This bit is read/write.

Default value: 0

This bit is available when MONO = 1.

CHSL = 0

L-channel selected (default)

CHSL = 1

R-channel selected

The CHSL bit is used to set the audio data selection for the monaural mode.

OS[1:0]

Delta-Sigma Oversampling Rate Selection

These bits are available for read/write.

Default value: 00

For DSD mode, this register is used to select the speed of BCK (pin 7) for the analog FIR filter.

OS[1:0]

Operation Speed Select

× (default)

Reserved

128

The OS bits are used to change the oversampling ratio of the delta-sigma modulator. This function is

useful when considering the output low-pass filter design that can handle a wide range of sampling

rates. As an example, selecting 128

× for f

S = 44.1 kHz, 64× for fS = 96 kHz, and 32× for fS = 192 kHz

operation would require a low-pass filter with a single cutoff frequency to accommodate all three

sampling rates.

B15

B14

B13

B12

B11

B10

RSV

ZFGR

ZFGL

Read Mode Control

Only set to 1 for read-back mode.

ZFGx

Zero Detection Flag

When x = L or R, corresponding to the DAC output channel.

These bits are available only for readback.

Default value: 00

ZFGx = 0

Not ZERO

ZFGx = 1

ZERO detected

When the PCM1738 detects that audio input data is continuously zero for 1024 LRCKs, the ZFGx bit

is set to 1 for the corresponding channel(s). Zero detect flags are also available at ZEROL (pin 2)

and ZEROR (pin 3).

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