ZSSC3230 Datasheet

R36DS0062ED0100 1.4

Jun 10, 2025

Page 32

© 2025 Renesas Electronics

NVM

Address

Word / Bi

t Range

Default

Setting

Word/ Bit Field

Name

Description

Configuration Register

19HEX

1:0

00BIN

CC_pin_selection

Defines which pin is used

for measurement (CC and/or CC’):

00  no input

01  CC

10 

CC’

11 

CC and CC’

2

0BIN

Dither

Enable/disable digital dithering to improve EMI performance:

0  No dithering

1  Dithering enabled

3

0BIN

En_sh2

Enable Subtraction Mode in grounded mode (see section 6.2.5):

0  Disabled

1  Enabled

4

0BIN

En_shlddrv

Enable active shield drive at the C0 pin (see section 6.2.4):

0  Disabled

1  Enabled

5

0BIN

Dyn_imp

Enables higher drive current in analog front end, which will be needed if the

sensor range is much smaller than the shift capacitor:

0  Disabled

1  Enabled

6

0BIN

Test_cap

Enables an internal reference sensor capacitor of approx. 2pF in parallel to

sensor input:

0  Disabled

1  Enabled

15:7

Reserved

Renesas lot tracking information; can be overwritten and used as free space

for customer use.

1AHEX

15:0

0000HEX

Reserved

Renesas lot tracking information; can be overwritten and used as free space

for customer use.

1BHEX

15:0

0000HEX

Reserved

Renesas lot tracking information; can be overwritten and used as free space

for customer use.

1CHEX

15:0

0000HEX

CRC

Generated checksum (CRC) for whole memory through a linear feedback shift

register (LFSR); Signature is checked upon power-up to ensure memory

content integrity

The NVM-consistency checksum is calculated (IC-internally for the whole NVM) using the polynomial: x16 + x15 + x2 + 1. The

checksum verification is only realized directly after VDD power-

on. If the checksum is successfully verified, then the “Memory

Error” status bit is set to 0BIN.