Getting to Know the Hardware

KTMPC5744DBUG Rev. 1.0 2/2015

Freescale Semiconductor, Inc.

9

3.4.4

Jumper and Switch Definitions

Table 5 defines the evaluation board jumper positions and explains their functions. For each jumper a default setting is shown on the left

side.

Table 5. Jumpers and Switches

Schematic Label

Setting

Description

JP1

INTb_SEL – selection of the MCU interrupt pin

1-2

INTb pin from the MC3390x is connected to a standard EIRQ interrupt pin of the MCU (PA0)

2-3

INTb pin from MC3390x is connected to the NMI (Non Maskable Interrupt) pin of the MCU

JP2

VPP_TEST – SoC Test Mode, See Table 6 for truth table

1-2

VPP_TEST pin is connected to the GND (Normal operation)

2-3

VPP_TEST pin is connected the VDD_HV_IO

JP3

RST_SBC – Connects RST coming from the SBC to the functional RESET of the MCU

JP4

ABS2 – puts Alternate Boot Selector bit 1 to the Ground (for all possible configurations see Table 6).

JP5

ABS1 – puts Alternate Boot Selector bit0 to the Ground (for all possible configurations see Table 6).

JP6

FAB – deactivates the Force Alternate Boot Mode (for all possible configurations see Table 6).

JP7

EXT_PORT – connects external Power On Reset of the MCU to an external port (to the mother board)