VA

AGND

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I/O

ADC12C080

SNAS379C – SEPTEMBER 2006 – REVISED APRIL 2013

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Dynamic Converter Electrical Characteristics at 65MSPS

Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = +3.0V, VDR = +2.5V, Internal VREF

= +1.2V, fCLK = 65 MHz, 50% Duty Cycle, DCS Disabled, VCM = VCMO, CL = 5 pF/pin, . Typical values are for TA = 25°C.

Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C

(1) (2)

Typical

Units

Symbol

Parameter

Conditions

Limits

(3)

(Limits) (4)

DYNAMIC CONVERTER CHARACTERISTICS, AIN= -1dBFS

fIN = 10 MHz

71.2

dBFS

SNR

Signal-to-Noise Ratio

fIN = 70 MHz

70.5

dBFS

fIN =170 MHz

68.5

dBFS

fIN = 10 MHz

90

dBFS

SFDR

Spurious Free Dynamic Range

fIN = 70 MHz

88

dBFS

fIN = 170 MHz

86

dBFS

fIN = 10 MHz

11.5

Bits

ENOB

Effective Number of Bits

fIN = 70 MHz

11.3

Bits

fIN = 170 MHz

11

Bits

fIN = 10 MHz

−88

dBFS

THD

Total Harmonic Disortion

fIN = 70 MHz

−85

dBFS

fIN = 170 MHz

−80

dBFS

fIN = 10 MHz

-100

dBFS

H2

Second Harmonic Distortion

fIN = 70 MHz

−95

dBFS

fIN = 170 MHz

−85

dBFS

fIN = 10 MHz

−90

dBFS

H3

Third Harmonic Distortion

fIN = 70 MHz

−88

dBFS

fIN = 170 MHz

−83

dBFS

fIN = 10 MHz

71.1

dBFS

SINAD

Signal-to-Noise and Distortion Ratio

fIN = 70 MHz

69.8

dBFS

fIN = 170 MHz

67.7

dBFS

POWER SUPPLY CHARACTERISTICS

IA

Analog Supply Current

Full Operation

90

mA (max)

IDR

Digital Output Supply Current

Full Operation (5)

14.5

mA

Power Consumption

Excludes IDR

(5)

270

mW (max)

(1)

The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided

current is limited per Note 4 under Absolute Maximum Ratings. However, errors in the A/D conversion can occur if the input goes above

2.6V or below GND as described in the Operating Ratings section.

(2)

With a full scale differential input of 2VP-P , the 12-bit LSB is 488 µV.

(3)

Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical

specifications are not ensured.

(4)

Parameters specified in dBFS indicate the value that would be attained with a full-scale input signal.

(5)

IDR is the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins,

the supply voltage, VDR, and the rate at which the outputs are switching (which is signal dependent). IDR=VDR(C0 x f0 + C1 x f1 +....C11 x

f11) where VDR is the output driver power supply voltage, Cn is total capacitance on the output pin, and fn is the average frequency at

which that pin is toggling.

10

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