R1 =

B

gm

GEA = gm x

VFB

VO

sR1C1 + 1

s x (sR1C1C2 + C1 + C2)

x

100

1k

10k

100k

1M

FREQUENCY (Hz)

-180

-150

-120

-90

-60

-30

0

100

1k

10k

100k

1M

FREQUENCY (Hz)

-60

-45

-30

-15

0

15

30

fSW

mC ± 0.5

ZL =

LM3495

SNVS410F – FEBRUARY 2006 – REVISED APRIL 2013

www.ti.com

And the higher frequency pole is:

(29)

In the equation for APS, the output resistance, RO, is the output voltage divided by output current. DC gain is

highest when output current is lowest. In order to design for the worst case, RO should be calculated for the

minimum load current. For this example, no minimum load has been specified, so a load of 100 mA will be used

(RO = 12Ω).

For this example, the value of DC gain is 24dB. The low frequency pole fP = ωP/ 2π is at 2.7kHz, the ESR zero fZ

=

ωZ/ 2π is at 1.06 MHz, and the higher frequency pole is at 48 kHz. Gain and phase plots for the power stage

are shown in Figure 37.

Figure 37. Power Stage Gain and Phase

The low frequency pole and higher frequency pole cause a roll-off in the gain of -20 dB/decade at lower

frequency that increases to -40 dB/decade at higher frequency. The effect of the ESR zero is not seen because

its frequency is beyond the switching frequency. If this loop were left uncompensated, the bandwidth would be 39

kHz and the phase margin 58°. This loop would be stable, but would suffer from poor regulation of the output

voltage due to the low DC gain. In practice, this loop could change significantly due to the tolerances in the

output inductor, output capacitor, changes in output current, or input voltage. Therefore, the loop is compensated

using the error amplifier and a few passive components.

In general the goal of the compensation circuit is to give high DC gain, a bandwidth that is between one-fifth and

one-tenth of the switching frequency, and at least 45° of phase margin. The majority of both peak current mode

and emulated peak current mode buck regulators can be compensated with just two components, R1 and C1, as

shown in the Typical Application Circuit. For power stages where the ESR zero frequency is below one-half of

the switching frequency a second capacitor, C2, may be needed to add another pole to the compensation. For

power stages where the ESR zero frequency is beyond the control loop bandwidth, a compromise in bandwidth

is needed to maintain good phase margin. The transfer function of the compensation block, GEA, can be derived

by multiplying the impedance ZC = (R1 + 1/sC1)ll( 1/sC2) times the DC gain of the error amp to give the following

equation:

(30)

This transfer function provides one pole at the origin, one zero at 1/(2

πR1C1), and another pole at approximately

1/(2

πR1C2) if C2 is used. If C2 is not used, a default value of 10 pF is substituted, representing the parasitic

capacitance from the COMP/SD pin to ground.

The value for R1 can be calculated using the following equation:

(31)

24

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