ZL40220

Data Sheet

13

Microsemi Corporation

3.3

Clock Outputs

LVDS has lower signal swing than LVPECL which results in a low power consumption. A simplified diagram for the

LVDS output stage is shown in Figure 13.

VDD

3 mA

Output

+

+

‐

‐

Figure 13 - Simplified LVDS Output Driver

The methods to terminate the ZL40220 drivers are shown in the following figures.

LVDS

Receiver

VDD

Zo = 50 Ohms

Zo = 50 Ohms

ZL40220

clk_p

clk_n

VDD_Rx

Figure 14 - LVDS DC Coupled Termination (Internal Receiver Termination)