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ADC31RF80IRMPT Datasheet(PDF) 45 Page - Texas Instruments

Part # ADC31RF80IRMPT
Description  ADC31RF80 3-GSPS Telecom Receiver and Feedback Device
PDF  142 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

ADC31RF80IRMPT Datasheet(HTML) 45 Page - Texas Instruments

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u
NCO
16
2949.12 MSPS
f
38230
1720.35 MHz
2
u S
NCO
16
DDCxNCOy
f
f
2
45
ADC31RF80
www.ti.com
SBAS860 – AUGUST 2017
Product Folder Links: ADC31RF80
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
8.3.4.3.12
Latency With Decimation Options
Table 4 describes device latency for different DDC options. At higher decimation options, latency increases
because of the increase in number of taps in the decimation filter.
Table 4. Latency With Different Decimation Options
DECIMATION OPTION
TOTAL LATENCY, DEVICE CLOCK CYCLES
Divide-by-4
516
Divide-by-6
746
Divide-by-8
621
Divide-by-9
763.5
Divide-by-10
811
Divide-by-12
897
Divide-by-16
1045
Divide-by-18
1164
Divide-by-20
1256
Divide-by-24
1443
Divide-by-32
1773
8.3.4.4 Numerically-Controlled Oscillators (NCOs) and Mixers
The ADC31RF80 is equipped with three independent, complex NCOs. Equation 2 shows how the oscillator
generates a complex exponential sequence.
x[n] = e
–jωn
where
•
frequency (ω) is specified as a signed number by the 16-bit register setting
(2)
The complex exponential sequence is multiplied by the real input from the ADC to mix the desired carrier down
to 0 Hz.
The ADC has two DDCs. The first DDC has three NCOs and the second DDC has one NCO. The first DDC can
dynamically select one of the three NCOs based on the GPIO pin or SPI selection. In wide-bandwidth mode
(lower decimation factors, for example, 4 and 6), there can only be one active DDC. The NCO frequencies can
be programmed independently through the DDCx, NCO[4:1], and the MSB and LSB register settings.
Equation 3 gives the NCO frequency setting that is set by the 16-bit register:
where
•
x = 0, 1
•
y = 1 to 4
(3)
For example:
If fS = 2949.12 MSPS, then the NCO register setting = 38230 (decimal).
Thus, Equation 4 defines fNCO:
(4)
Any register setting changes that occur after the JESD204B interface is operational results in a non-deterministic
NCO phase. If a deterministic phase is required, the JESD204B interface must be reinitialized after changing the
register setting.
8.3.5 NCO Switching
The first DDC (DDC0) provides three different NCOs that can be used for phase-coherent frequency hopping.
This feature is available in both single-band and dual-band mode, but only affects DDC0.



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