| Electronic Components Datasheet Search |
|
ADC31RF80IRMPT Datasheet(PDF) 53 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
ADC31RF80IRMPT Datasheet(HTML) 53 Page - Texas Instruments |
|
53 / 142 page ![]() JESD204B Long Transport Layer Test Pattern Data Mapping Frame Construction 8b, 10b Encoding JESD204B Link Layer Test Pattern Serializer ADC Section Transport Layer Link Layer PHY Layer Interleaving Engine Digital Block ADC Scrambler 1 + x 14 + x15 12-bit RAMP Test Patterns Decimation Filter Block DDC To GPIO AGC Pins OUTSEL GPIO[4:1] IIR PK DET0 [2] IIR PK DET1 [2] BLKPKDETH [1] BLKPKDETL [1] FOVR PWR DET [2] 53 ADC31RF80 www.ti.com SBAS860 – AUGUST 2017 Product Folder Links: ADC31RF80 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 8.3.8.4 GPIO AGC MUX The GPIO pins can be used to control the NCO in wideband DDC mode or as alarm outputs. Figure 129 shows that the GPIO pins can be configured through the SPI control to output the alarm from the peak power (1 bit), crossing detector (1 or 2 bit), faster overrange, or the RMS power output. The programmable output MUX allows connecting any signal (including the NCO control) to any of the four GPIO pins. These pins can be configured as outputs (AGC alarm) or inputs (NCO control) through SPI programming. Figure 129. GPIO Output MUX Implementation 8.3.9 Power-Down Mode The ADC31RF80 provides a lot of configurability for the power-down mode. Power-down can be enabled using the PDN pin or the SPI register writes. 8.3.10 ADC Test Pattern The ADC31RF80 provides several different options to output test patterns instead of the actual output data of the ADC in order to simplify the serial interface and system debug of the JESD204B digital interface link. Figure 130 shows the output data path. Figure 130. Test Pattern Generator Implementation 8.3.10.1 Digital Block The ADC test pattern replaces the actual output data of the ADC. The test patterns listed in Table 11 are available when the DDC is enabled and located in register 37h of the decimation filter page. When programmed, the test patterns are output for each converter (M) stream. The number of converter streams increases by 2 when complex (I, Q) output or dual-band DDC is selected. Additionally, a 12-bit test pattern is also available. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |