AMC1306M25 datasheet(25/45 Pages) TI2

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Clock

Uncoded

Bitstream

Machester

Coded

Bitstream

Clipping

2 V

ModulatorOutput

AnalogInput

+FS(AnalogInput)

-FS(AnalogInput)

AMC1306E05, AMC1306E25, AMC1306M05, AMC1306M25

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SBAS734C – MARCH 2017 – REVISED JANAURY 2020

Product Folder Links: AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25

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Feature Description (continued)

8.3.4 Digital Output

A differential input signal of 0 V ideally produces a stream of ones and zeros that are high 50% of the time. A

differential input of 250 mV (for the AMC1306x25) or 50 mV (for the AMC1306x05) produces a stream of ones

and zeros that are high 89.06% of the time. With 16 bits of resolution, that percentage ideally corresponds to the

code 58368. A differential input of –250 mV (–50 mV for the AMC1306x05) produces a stream of ones and zeros

that are high 10.94% of the time and ideally results in code 7168 with 16-bit resolution. These input voltages are

also the specified linear ranges of the different AMC1306 versions with performance as specified in this

document. If the input voltage value exceeds these ranges, the output of the modulator shows nonlinear behavior

when the quantization noise increases. The output of the modulator clips with a stream of only zeros with an

input less than or equal to –320 mV (–64 mV for the AMC1306x05) or with a stream of only ones with an input

greater than or equal to 320 mV (64 mV for the AMC1306x05). In this case, however, the AMC1306 generates a

single 1 (if the input is at negative full-scale) or 0 every 128 clock cycles to indicate proper device function (see

the Fail-Safe Output section for more details). The input voltage versus the output modulator signal is shown in

Figure 51.

Figure 51. Analog Input versus the AMC1306 Modulator Output

The density of ones in the output bitstream for any input voltage value (with the exception of a full-scale input

signal, as described in the Output Behavior in Case of a Full-Scale Input section) can be calculated using

Equation 1:

(1)

The AMC1306 system clock is provided externally at the CLKIN pin. For more details, see the Switching

Characteristics table and the Manchester Coding Feature section.

8.3.5 Manchester Coding Feature

The AMC1306Ex offers the IEEE 802.3-compliant Manchester coding feature that generates at least one

transition per bit to support clock signal recovery from the bitstream. A Manchester coded bitstream is free of dc

components. The Manchester coding combines the clock and data information using exclusive or (XOR) logical

operation and results in a bitstream as shown in Figure 52. The duty cycle of the Manchester encoded bitstream

depends on the duty cycle of the input clock CLKIN.

Figure 52. Manchester Coded Output of the AMC1306Ex

AMC1306M25 Datasheet(PDF) 25 Page - Texas Instruments

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