STAMP0 datasheet(12/62 Pages) STMICROELECTRONICS

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Electrical specifications

STAMP0

12/62

DocID028639 Rev 1

3.3

Electrical characteristics

The values listed in the table below are specified for VDD = 3.3 V, VDD_PLL = 3.3 V and

Tamb = 25 °C, unless otherwise stated.

Table 5: Electrical specifications

Symbol

Parameter

Test condition

Min.

Typ.

(1)

Max.

Unit

VDD

Supply voltage

3.0

3.3

3.6

VDD_PLL

PLL supply voltage

3.0

3.3

3.6

IDD

Operating current

clk = mckl = 100 MHz

VDD = 3.6 V

VDD_PLL= 3.6 V

IDD_STBY

Standby current

VDD = 3.6 V

2.5

VDD_PLL = 3.6 V

450

µA

Digital IO characteristics

VIH

High-level input voltage

VIL

Low-level input voltage

0.8

VOH

High-level output voltage

VDD-0.15

VOL

Low-level output voltage

0.15

VHYST

Schmitt trigger hysteresis

400

RDW

Pull-down resistance

(@Vi = VDD)

120

IIH/IIL

Input pad leakage

-2

0.02

µA

PLL characteristics

CLK_IN

Input clock frequency

range

2.048

49.152

MHz

D_IN

Input clock duty cycle

RT_IN

Clock in rise time

0.2

FT_IN

Clock in fall time

0.2

INF_IN

Phase comparator freq.

range

FRAC CTRL=0

2.048

16.384

MHz

FRAC CTRL=1

2.048

12.288

MHz

FVCO

PLL output frequency

65.536

98.304

MHz

Free-running

(CLCKIN=0)

MHz

PKVCO

Peal overshoot in VCO

freq.

DVCO

FVCO duty cycle

Lock time

200

µs

PLL_BW

PLL bandwidth

5 < NDIV < 31

2040/NDIV

4705/NDIV

kHz

32 < NDIV < 48

149

kHz

JPK

Jitter peaking at BW

Notes:

(1)

Typical specifications are not guaranteed.

Obsolete

Product(s)

- Obsolete

Product(s)

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