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STM32WL33C8 Datasheet(PDF) 68 Page - STMicroelectronics |
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STM32WL33C8 Datasheet(HTML) 68 Page - STMicroelectronics |
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68 / 91 page  6.3.17 ADC characteristics Table 59. ADC characteristics (HSI must be set to PLL mode) Symbol Parameter Conditions Min. Typ. Max Units Channels Diff Number of channels for differential mode VFQFPN48 , VFQFPN32 - - 4 - Channels SE Number of channels for single ended mode VFQFPN48 , VFQFPN32 - - 8 - IBATADCBIAS ADC biasing consumption at battery Biasing blocks turned on - 145 - µA IBATADCACTIVE ADC active consumption at battery ADC activated in differential mode - 185 - µA RAIN Input impedance In DC - 250 - kΩ Rin Internal access resistance VBOOST is enabled for VBAT < 2.7 V - - 550 Ω Cin Input sampling capacitor - - 4 - pF Ts Sampling period Default config - 1 - µs Tsw Sampling time Default config - 125 - ns DR Output data rate - - 200 - ksamples/s FRMToutput Output data format - - 16 - bits TL Latency time 200 ks/s - 5 - µs TsTARTUP Start up time From ADC Enable to conversion start - - 1 µs DNL Differential non -linearity - - +/-0.7 - LSB INL Integral non-linearity - - +/-1 - LSB SNR Diff Signal to noise ratio Differential input @1 kHz, -1 dBFs, Fs = 800 kHz, DS=4 - 72 - dB STHD Diff Signal to THD ratio (10 harmonics) Differential input @1 kHz, -1 dBFs, Fs = 800 kHz, DS=4 - 75 - dB ENOB Diff Effective number of bits Differential input @1 kHz, -1 dBFs, Fs = 800 kHz, DS=4 - 11.5 - bits SNR SE Signal to noise ratio Single ended @1 kHz, -1 dBFs, Fs = 800 kHz, DS=4 - 70 - dB STHD SE Signal to THD ratio (10 harmonics) Single ended @1 kHz, -1 dBFs, Fs = 800 kHz, DS=4 - 70 - dB ENOB SE Effective number of bits Single ended @1 kHz, -1 dBFs, Fs = 800 kHz, DS=4 - 11 - bits ADC ERROR ADC_ERR_1V7 Absolute error when used for battery measurement at 1.7 V, 2.4 V, 3.0 V, 3.6 V - 13 - mV ADC_ERR_2V4 - 0 - mV ADC_ERR_3V0 - -9 - mV ADC_ERR_3V6 - -22 - mV STM32WL33xx Electrical characteristics DS14221 - Rev 5 page 68/91 |
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