STM32WL33C8 datasheet(22/91 Pages) STMICROELECTRONICS

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3.13

Advanced encryption standard hardware accelerator (AES)

The AES hardware accelerator can be used to both encrypt and decrypt data using the AES algorithm. It is a fully

compliant implementation of the advanced encryption standard (AES) as defined by Federal Information

Processing Standards Publication (FIPS PUB 197, 2001 November 26). Multiple key sizes and chaining modes

are supported: ECB, CBC, CTR for key sizes of 128 bits The AES is a 32-bit AHB peripheral. It supports DMA

single transfers for incoming and outgoing data (two DMA channels required). The AES IP provides hardware

acceleration to AES crypto algorithm packaged in STM32WL33xx crypto library (excluding key length of 192-bit).

The main features of the AESare:

•

NIST FIPS publication 197, Advanced Encryption Standard (AES) compliant implementation

•

128-bit data block processing

•

Support for cipher keys length of 128-bit

•

Encryption and decryption with multiple chaining modes: – Electronic Code Book (ECB) – Cipher Block

Chaining (CBC) – Counter Mode (CTR)

•

51 clock cycles for processing one 128-bit block of data with a 128-bit key in ECB mode

•

Integrated key scheduler with its key derivation stage (ECB or CBC decryption only)

•

32-bit AHB interface for register accesses, supporting complete word access only (32- bit). NB: AHB

sequential accesses are not supported.

•

128-bit registers for storing initialization vectors (4× 32-bit)

•

1x32-bit INPUT buffer and 1x32-bit OUTPUT buffer

•

Automatic data flow control with support of direct memory access (DMA) using two channels (one for

incoming data, one for processed data). Single transfers only.

•

Data swapping logic to support 1-bit, 8-bit, 16-bit or 32-bit data

•

Possibility for software to suspend a message if the IP needs to process another message with a higher

priority (context swapping)

3.14

True random number generator (RNG)

The RNG is a random number generator based on a continuous analog noise that provides a 16-bit value to the

host when read.

3.15

Cyclic redundancy check (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator

with polynomial value and size. Among other applications, the CRC-based techniques are used to verify data

transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a mean to verify the

flash memory integrity. The CRC calculation unit helps to compute a signature of the software during runtime,

which can later be compared with a reference signature generated at link-time, and which can be stored at a

given memory location.

STM32WL33xx

Functional overview

DS14221 - Rev 5

page 22/91

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