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DP83867IRPAPR Datasheet(PDF) 49 Page - Texas Instruments

Part # DP83867IRPAPR
Description  DP83867IR/CR Robust, High Immunity 10/100/1000 Ethernet Physical Layer Transceiver
PDF  139 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

DP83867IRPAPR Datasheet(HTML) 49 Page - Texas Instruments

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For further detail relating to the latch-in timing requirements of the PHY Address pins, as well as the other
hardware configuration pins, refer to Section 7.5.5.
Based on the default strap configuration of PHY_ADD[4:0], the DP83867 PHY address initializes to 0x00 without
any external strap configuration.
Refer to Figure 7-15 for an example of a PHY address connection to external components. In this example, the
pins are configured as follows: RX_D4 = Strap Mode 4, RX_D2 = Strap Mode 3, and RX_D0 = Strap Mode 2.
Therefore, the PHY address strapping results in address 11001 (19h).
10 k
2.49 k
VDDIO
RX_D0
5.76 k
2.49 k
VDDIO
RX_D2
2.49 k
RX_D4
VDDIO
Figure 7-15. IRPAP PHY Address Strapping Example
Refer to Figure 7-16 for an example of a PHY address connection to external components. In this example, the
pins are configured as follows: RX_D2 = Strap Mode 3 and RX_D0 = Strap Mode 2. Therefore, the PHY address
strapping results in address 1001 (09h).
www.ti.com
DP83867IR, DP83867CR
SNLS484I – FEBRUARY 2015 – REVISED JANUARY 2025
Copyright © 2025 Texas Instruments Incorporated
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Product Folder Links: DP83867IR DP83867CR



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