SPC563M60X datasheet(11/128 Pages) STMICROELECTRONICS

11 / 128 page

DocID14642 Rev 12

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SPC563M64x, SPC563M60x

Overview

127

– Software controlled clock gating of peripherals

– Low power stop mode, with all clocks stopped

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Fabricated in 90 nm process

–

1.2 V internal logic

–

Single power supply with 5.0 V

5 % (4.5 V to 5.25 V) with internal

regulator to provide 3.3 V and 1.2 V for the core

–

Input and output pins with 5.0 V

5% (4.5 V to 5.25 V) range

35 %/65 % VDDE CMOS switch levels (with hysteresis)

– Selectable hysteresis

– Selectable slew rate control

–

Nexus pins powered by 3.3 V supply

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Designed with EMI reduction techniques

– Phase-locked loop

– Frequency modulation of system clock frequency

– On-chip bypass capacitance

– Selectable slew rate and drive strength



High performance e200z335 core processor

–

32-bit Power Architecture Book E programmer’s model

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Variable Length Encoding Enhancements

– Allows Power Architecture instruction set to be optionally encoded in a mixed

16 and 32-bit instructions

– Results in smaller code size

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Single issue, 32-bit Power Architecture technology compliant CPU

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In-order execution and retirement

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Precise exception handling

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Branch processing unit

– Dedicated branch address calculation adder

– Branch acceleration using Branch Lookahead Instruction Buffer

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Load/store unit

– One-cycle load latency

– Fully pipelined

– Big and Little Endian support

– Misaligned access support

– Zero load-to-use pipeline bubbles

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Thirty-two 64-bit general purpose registers (GPRs)

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Memory management unit (MMU) with 16-entry fully-associative translation look-

aside buffer (TLB)

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Separate instruction bus and load/store bus

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Vectored interrupt support

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Interrupt latency < 120 ns @ 80 MHz (measured from interrupt request to

execution of first instruction of interrupt exception handler)

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