SPC563M60X datasheet(110/128 Pages) STMICROELECTRONICS

110 / 128 page

Electrical characteristics

SPC563M64x, SPC563M60x

110/128

DocID14642 Rev 12

tHI

Data Hold Time for Inputs

Master (MTFE = 0)

–4

—

–4

—

–4

—

Slave

7—7—7—

Master (MTFE = 1,

CPHA = 0)(7)

—

Master (MTFE = 1,

CPHA = 1)

–4

—

–4

—

–4

—

tSUO

Data Valid (after SCK edge)

Master (MTFE = 0)

—6—6—6

Slave

—25—25

—25

Master (MTFE = 1,

CPHA=0)

—45—25

—21

Master (MTFE = 1,

CPHA=1)

—6—6—6

tHO

Data Hold Time for Outputs

Master (MTFE = 0)

–5

—

–5

—

–5

—

Slave

5.5

—

5.5

—

5.5

—

Master (MTFE = 1,

CPHA = 0)

8—4—3—

Master (MTFE = 1,

CPHA = 1)

–5

—

–5

—

–5

—

All DSPI timing specifications use the fastest slew rate (SRC = 0b11) on pad type M or MH. DSPI signals using pad types of

S or SH have an additional delay based on the slew rate. DSPI timing is specified at VDDEH = 3.0–5.25 V, TA = TL to TH,

and CL = 50 pF with SRC = 0b11.

Speed is the nominal maximum frequency. Max speed is the maximum speed allowed including frequency modulation

(FM). 42 MHz parts allow for 40 MHz system clock + 2% FM; 66 MHz parts allow for a 64 MHz system clock + 2% FM, and

82 MHz parts allow for 80 MHz system clock + 2% FM.

The minimum DSPI Cycle Time restricts the baud rate selection for given system clock rate. These numbers are calculated

based on two SPC563Mxx devices communicating over a DSPI link.

The actual minimum SCK cycle time is limited by pad performance.

The maximum value is programmable in DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK].

The maximum value is programmable in DSPI_CTARx[PASC] and DSPI_CTARx[ASC].

This number is calculated assuming the SMPL_PT bitfield in DSPI_MCR is set to 0b10.

Table 41. DSPI timing(1)(2) (continued)

Symbol

Characteristic

40 MHz

64 MHz

80 MHz

Unit

Min

Max

Min

Max

Min

Max

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