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SPC563M60L7 Datasheet(PDF) 100 Page - STMicroelectronics |
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SPC563M60L7 Datasheet(HTML) 100 Page - STMicroelectronics |
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100 / 128 page ![]() Electrical characteristics SPC563M64x, SPC563M60x 100/128 DocID14642 Rev 12 Figure 6. JTAG test clock input timing 14 tBSDST CC D Boundary Scan Input Valid to TCK Rising Edge 50 — ns 15 tBSDHT CC D TCK Rising Edge to Boundary Scan Input Invalid 50 — ns 1. JTAG timing specified at VDD = 1.14 V to 1.32 V, VDDEH = 4.5 V to 5.25 V with multi-voltage pads programmed to Low- Swing mode, TA = TL to TH, and CL = 30 pF with DSC = 0b10, SRC = 0b00. These specifications apply to JTAG boundary scan only. See Table 38 for functional specifications. Table 37. JTAG pin AC electrical characteristics(1) (continued) # Symbol C Characteristic Min. Value Max. Value Unit TCK 1 2 2 3 3 |
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