TLC5948APWPR.B datasheet(31/54 Pages) TI2

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TLC5948A

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SBVS192A – MARCH 2012 – REVISED DECEMBER 2012

Function Control (FC) Data Latch

The FC data latch is 13 bits long. This latch enables the constant-current outputs, enables the auto display

repeat and display timing reset functions, and sets the PWM control mode and the LOD, LSD, and OLD data

latch timing. Each function is selected by the first control data latch. When the device is powered on, the data of

the FC data in the first control data latch are random (except the BLANK and PSMODE bits) in order to disable

all constant-current outputs. The FC data bit assignment in the first control data latch is shown in Table 10.

Table 10. Function Control Data Latch Bit Description

DEFAULT

BIT

VALUE

NUMBER

NAME

(Binary)

DESCRIPTION

Constant-current output blank bit

0 = On, 1 = Off

When this bit is '0', all constant-current outputs (OUT0-OUT15) are controlled

119

BLANK

by the GS PWM timing controller.

When this bit is '1', all constant-current outputs are forced off, the GS counter is

reset to '0', and the GS PWM timing controller is initialized. When the device is

powered on, this bit is set to '1'.

Auto display repeat mode enable bit

0 = Disabled, 1 = Enabled

When this bit is '0', the auto display repeat function is disabled. Each constant-

120

DSPRPT

—

current output is turned on and off for one display period after the BLANK bit is

set to '0'.

When this bit is '1', each output is repeated every 65536 GS clocks. When the

device is powered on, this bit is random.

Display timing reset mode enable bit

0 = Disabled, 1 = Enabled

When this bit is '0', the GS counter is not reset and the outputs are not forced

off even with a LAT rising edge.

121

TMGRST

—

When this bit is '1', the GS counter is reset to '0' and all outputs are forced off

at the LAT rising edge for a GS data write. This function is identical to the

BLANK bit. Therefore, a BLANK bit data change is not needed to control the

outputs from a controller. PWM control resumes from the next GSCLK rising

edge. When the device is powered on, this bit is random.

ES-PWM mode enable bit

0 = Disabled, 1 = Enabled

When this bit is '0', the conventional PWM control mode is selected.

122

ESPWM

—

When this bit is '1', ES-PWM control mode is selected. If the TLC5948A is used

for multiplexing a drive, the conventional PWM mode should be selected to

prevent excess on/off switching. When the device is powered on, this bit is

random.

LOD detection voltage selection bits

LED open detection (LOD) detects a fault caused by an open LED by

123, 124

LODVLT

—

comparing the OUTn voltage to the LOD detection threshold voltage. The

threshold voltage is selected with these bits. Refer to Table 11 for the detect

voltage truth table. When the device is powered on, this bit is random.

LSD detection voltage selection bits

LED short detection (LSD) detects a fault caused by a shorted LED by

125, 126

LSDVLT

—

comparing the OUTn voltage to the LSD detection threshold voltage. The

threshold voltage is selected by these bits. Refer to Table 12 for the detect

voltage truth table. When the device is powered on, this bit is random.

LOD and LSD data reading timing selection bits

The LOD and LSD data reading time is selected by these bits.

When DSPRPT is '1' and IDMRPT is '0', LOD and LSD data are loaded to the

127, 128

LATTMG

—

LOD and LSD data latch only once after new GS data are written into the

second GS data latch. Refer to Table 13 for the data load timing truth table.

When the device is powered on, this bit is random.

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