TLV172IDCKT.B datasheet(14/49 Pages) TI2

14 / 49 page

Frequency (Hz)

100

110

120

130

140

150

160

10M

100M

10G

D018

10k

100k

10M

Frequency (Hz)

C033

Maximum output voltage without

slew-rate induced distortion.

VS = ±15 V

VS = ±5 V

VS = ±2.25 V

Temperature (qC)

-75

-50

-25

100

125

150

100

D010

ISC, Sink ±18 V

ISC, Source ±18 V

-20

-15

-10

-5

0.5

1.5

2.5

3.5

4.5

Time (s)

C034

0.1% Settling = ±10 mV

Time (500 ns/div)

D005

-18 V

+18 V

RF = 1 NW

RI = 1 NW

VIN = 10 V

-20

-15

-10

-5

0.5

1.5

2.5

3.5

4.5

Time (s)

C034

0.1% Settling = ±10 mV

TLV172, TLV2172, TLV4172

SBOS784C – NOVEMBER 2016 – REVISED JANUARY 2019

www.ti.com

Product Folder Links: TLV172 TLV2172 TLV4172

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at VS = ±18 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)

RL = 1 kΩ

CL = 10 pF

Figure 19. Large-Signal Step Response

10-V positive step

G = 1

CL = 10 pF

Figure 20. Large-Signal Settling Time

10-V negative step

G = 1

CL = 10 pF

Figure 21. Large-Signal Settling Time

Figure 22. Short-Circuit Current vs Temperature

Figure 23. Maximum Output Voltage vs Frequency

PRF = –10 dBm

VSUPPLY = ±18 V

VCM = 0 V

Figure 24. EMIRR IN+ vs Frequency

TLV172IDCKT.B Datasheet(PDF) 14 Page - Texas Instruments

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