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TLV172IDCKT.B Datasheet(PDF) 20 Page - Texas Instruments |
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TLV172IDCKT.B Datasheet(HTML) 20 Page - Texas Instruments |
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20 / 49 page ![]() LOAD ISO o ISO LOAD 1 + C × R × s T(s) = 1 + R + R × C × s CLOAD + ± VIN VOUT +VS RISO -VS Copyright © 2017, Texas Instruments Incorporated 20 TLV172, TLV2172, TLV4172 SBOS784C – NOVEMBER 2016 – REVISED JANUARY 2019 www.ti.com Product Folder Links: TLV172 TLV2172 TLV4172 Submit Documentation Feedback Copyright © 2016–2019, Texas Instruments Incorporated 9 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 9.1 Application Information The TLVx172 operational amplifier provides high overall performance in a large number of general-purpose applications. As with all amplifiers, applications with noisy or high-impedance power supplies require decoupling capacitors placed close to the device pins. In most cases, 0.1-µF capacitors are adequate. Follow the additional recommendations in the Layout Guidelines section to achieve the maximum performance from this device. Many applications introduce capacitive loading to the output of the amplifier (which potentially causes instability). To stabilize the amplifier, add an isolation resistor between the amplifier output and the capacitive load. Typical Application section shows the process for selecting a resistor. 9.2 Typical Application This circuit can drive capacitive loads (such as cable shields, reference buffers, MOSFET gates, and diodes). The circuit uses an isolation resistor (RISO) to stabilize the output of an operational amplifier. RISO modifies the open-loop gain of the system to ensure that the circuit has sufficient phase margin. Figure 29. Unity-Gain Buffer With RISO Stability Compensation 9.2.1 Design Requirements The design requirements are: • Supply voltage: 30 V (±15 V) • Capacitive loads: 100 pF, 1000 pF, 0.01 μF, 0.1 μF, and 1 μF • Phase margin: 45° and 60° 9.2.2 Detailed Design Procedure Figure 29 shows a unity-gain buffer driving a capacitive load. Equation 1 shows the transfer function for the circuit in Figure 29.Figure 29 does not show the open-loop output resistance of the operational amplifier (Ro). (1) The transfer function in Equation 1 has a pole and a zero. The frequency of the pole (fp) is determined by (Ro + RISO) and CLOAD. The RISO and CLOAD components determine the frequency of the zero (fz). A stable system is obtained by selecting RISO so that the rate of closure (ROC) between the open-loop gain (AOL) and 1/β is 20 dB per decade. Figure 30 shows the concept. The 1/β curve for a unity-gain buffer is 0 dB. |
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