AFE10004RGETEP datasheet(45/159 Pages) TI2

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6.5 Programming

Note

In SPI configuration, hold the SDA pin low for proper operation.

The device communicates with the system controller through a serial interface, which supports either an I2C-

compatible two-wire bus, or an SPI-compatible bus. The device includes a robust mechanism that detects

between an SPI-compatible or I2C-compatible controller, and automatically configures the interface accordingly.

The interface detection mechanism operates at start-up, thus preventing protocol change during normal

operation.

The device uses a paging system to organize registers by functionality. In both SPI and I2C configurations,

address 0x7E is used to select the different pages in the device. The default page at start-up is Page 1. To read

and write to one of the device registers, first select the page for that register by writing the 8-bit representation

of the page number (PAGE[7:0]) to address 0x7E. Figure 6-17 shows the page access format. The page register

holds the page value until a new page address is programmed to the device.

TargetAddr[6:0]

RegAddr[7:0]

0x7E

Data[7:0]

PAGE[7:0]

From Controller to Peripheral (SPI) or Target (I

2C)

From Target to Controller

RegAddr[6:0]

0x7E

Data[15:8]

PAGE[7:0]

Data[7:0]

0x00

SPI

Figure 6-17. Page Access Format

6.5.1 I2C Serial Interface

In I2C mode, the device operates only as a target device on the two-wire bus. Connections to either bus

are made using the open-drain I/O lines, SDA and SCL. The SDA and SCL pins feature integrated spike

suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. The device

supports the transmission protocol for fast (1kHz to 400kHz) mode. All data bytes are transmitted MSB first.

6.5.1.1 I2C Bus Overview

The device is I2C compatible. In I2C protocol, the device that initiates the transfer is called a controller, and the

devices controlled by the controller are targets. To control the bus, use a controller device that generates the

serial clock (SCL), controls the bus access, and generates the START and STOP conditions.

To address a specific device, a START condition is initiated. A START condition is indicated by pulling the data

line (SDA) from a high-to-low logic level while SCL is high. All targets on the bus shift in the target address byte,

with the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the target

being addressed responds to the controller by generating an acknowledge bit and pulling SDA low.

Data transfer is then initiated and sent over eight clock pulses followed by an acknowledge bit. During data

transfer, ensure that SDA remains stable while SCL is high because any change in SDA while SCL is high is

interpreted as a control signal.

After all data have been transferred, the controller generates a STOP condition. A STOP condition is indicated

by pulling SDA from low to high, while SCL is high.

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AFE10004-EP

SLASFM1A – JUNE 2025 – REVISED DECEMBER 2025

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