CY2SSTV8575

Rev 1.0, November 25, 2006

Page Page 3 of

Power Management Functions

Output enable/disable control of the CY2SSTV8575 allows the

user to implement power management schemes into the

design. Outputs are three-stated/disabled when OE is

asserted low, see Table 1. The enabling and disabling of

outputs is done in such a manner to eliminate the possibility of

the partial “runt” clocks.

Zero Delay Buffer

When used as a zero delay buffer the CY2SSTV8575 will likely

be in a nested clock tree application. For these applications

the CY2SSTV8575 offers a differential clock input pair as a

PLL reference. The CY2SSTV8575 can lock onto the

reference and translate with near zero delay to low-skew

outputs. For normal operation, the external feedback input,

FBIN, is connected to the feedback output, FBOUT. By

connecting the feedback output to the feedback input the

propagation delay through the device is eliminated. The PLL

works to align the output edge with tine input reference edge

thus producing a near zero delay. The reference frequency

affects the static phase offset of the PLL and thus the relative

delay between the inputs and outputs.

When AVDD is strapped LOW, the PLL is turned off and

bypassed for test purposes.

Note:

1. Output load capacitance for 2 DDR-SDRAM loads: 5 pF < CL < 8 pF.

PLL

FBIN

FBIN#

120 Ohm

120 Ohm

CLK

CLK#

DDR -

SDRAM

120 Ohm

VTR

VCP

0.3"

= 2.5"

= 0.6" (Split to Terminator)

DDR _SDRAM

represents a capacitive

load

DDR -

SDRAM

FBOUT#

FBOUT

Yx

Yx#