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CY2SSTV8575ACT Datasheet(PDF) 4 Page - SpectraLinear Inc |
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CY2SSTV8575ACT Datasheet(HTML) 4 Page - SpectraLinear Inc |
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4 / 7 page ![]() CY2SSTV8575 Rev 1.0, November 25, 2006 Page Page 4 of Figure 2. Clock Structure 2[2] Figure 3. Differential Signal Using Direct Termination Resistor Governing Agencies The following agencies provide specifications that apply to the CY2SSTV8575. The agency name and relevant specification is listed below; Agency Name ....................................................................... Specification JEDEC................................................................. MS - 026-C Note: 2. Output load capacitance for 4 DDR-SDRAM loads: 10 pF < CL < 16 pF. DDR-SDRAM PLL FBIN FBIN# 120 Ohm 120 Ohm CLK CLK# DDR-SDRAM Stack DDR-SDRAM Stack 120 Ohm VTR VCP 0.3" = 2.5" = 0.6" (Split to Terminator) DDR-SDRAM represents a capacitive load FBOUT# FBOUT DDR-SDRAM DDR-SDRAM DDR-SDRAM Yx# Yx 60 O hm Receiver VC P VT R R T = 120 O h m VDD OU T OU T # VD D 60 O hm 14 pF 14 pF VDD /2 VDD/2 |
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