25CS160-ISLASHST datasheet(22/53 Pages) MICROCHIP

22 / 53 page

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Preliminary

DS20007008B-page 22

25CS160

FIGURE 6-1:

READ STATUS REGISTER (

RDSR) SEQUENCE

6.3

Write STATUS Register (WRSR)

The Write STATUS Register (WRSR) instruction enables

the SPI host to change selected bits of the STATUS

WREN instruction must be executed to set the WEL bit

to logic ‘1’. Upon completion of a WREN instruction, a

WRSR sequence can be executed.

The WRSR instruction will only modify:

• Byte 0: bit 7, bit 3 and bit 2

These modifiable bits are the Write-Protect Enable

(WPEN) bit and the Block Protect (BP1, BP0) bits.

These three bits are nonvolatile and have the same

properties and functions as regular EEPROM bits.

Their values are retained while power is removed from

the device.

The 25CS160 will not respond to instructions other

than a RDSR or a WRSR sequence until the self-timed

internal write cycle has completed. When the write

cycle has completed, the WEL bit in the STATUS

FIGURE 6-2:

WRITE STATUS REGISTER (

WRSR) SEQUENCE

9 1011

1415

SCK

00000 101

RDSR Opcode (05h)

12 13

16 17 18 19 20 21 22 23

D4 D3 D2 D1 D0

STATUS Register Byte 0

STATUS Register Byte 1

High-Impedance

D4 D3 D2 D1 D0

Note:

If the CS pin is deasserted anywhere

other than the end of an 8-bit byte

boundary, the sequence will be aborted,

and no write cycle will take place.

910 11

14 15

SCK

12 13

16 17 18 19 20 21 22 23

High-Impedance

0 0 0 00001 D7 XX

X D3 D2 X X

X X XXX

X X X

WRSR Opcode (01h)

STATUS Register Byte 0

STATUS Register Byte 1

MSb

TWC(1)

Note 1: This sequence initiates a self-timed internal write cycle on the rising edge of CS after a valid sequence.

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