25CS160-ISLASHST datasheet(27/53 Pages) MICROCHIP

27 / 53 page

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Preliminary

DS20007008B-page 27

25CS160

9.1.1

READING THE

FACTORY-PROGRAMMED 128-BIT

SERIAL NUMBER

The Security register contains a factory-programmed,

globally unique, read-only 128-bit serial number. This

serial number is unique across all varieties of Microchip

CS series EEPROM, and it is located in the lower 16

bytes of the Security register (bytes 0h-Fh). Reading

the serial number is accomplished in the same way as

the reading of any other data in the Security register.

9.2

Writing to the Security Register

Executing a write sequence to the Security register is

identical to writing to the EEPROM, as described in

Section 8.1.1 “Byte Write” and Section 8.1.2 “Page

Write”, with the exception that the WREX (82h)

instruction is used while A10 must be a logic ‘0’ and A5

must be a logic '1' to write the user-programmable,

lockable ID page. In Legacy Write Protection mode, the

Security register is write-protected when the BP[1:0]

bits (bits 3-2, byte 0) of the STATUS register = 11.

There is no dependency on the WPEN bit (bit 7, byte 0)

of the STATUS register or the WP pin.

The user-programmable, lockable ID page of the

Security register can also be permanently locked,

making its contents read-only. This is accomplished

with the LOCK instruction. The CHLK instruction can

determine if the device has been previously locked. If

the Security register is locked, any subsequent WREX

instructions will be ignored.

9.2.1

LOCKING THE SECURITY

The upper 32 bytes of the Security register are shipped

by Microchip in a user-programmable state. Once the

desired data are written, the user-programmable,

lockable ID page of the Security register can be

permanently write-protected with the LOCK instruction.

The LOCK instruction is irreversible and will

permanently prevent all future write sequences to the

upper 32 bytes of the Security register on the

25CS160, thereby rendering the entire 64-byte

Security register read-only.

The LOCK instruction emulates a write sequence in that

a WREN instruction must first be sent to set the WEL bit

in the STATUS register to logic ‘1’. As shown in

Figure 9-4, the LOCK (82h) instruction is clocked in on

the SI line, followed by a dummy address where bits

A15 through A0 are “don't care” bits, with the exception

that bit A10 must be set to logic ‘1’. Finally, a

confirmation data byte of xxxxxx1xb is sent, and the

self-timed internal write cycle will begin once the CS pin

is driven high.

Note:

To ensure a unique number, the 128-bit

serial number must be read from the

starting address. Additionally, the entire

serial number must be read to realize a

completely unique value.

Note:

If the CS pin is deasserted anywere other

than at the end of an 8-bit byte boundary,

the sequence will be aborted, and no write

cycle will take place.

Note:

The LOCK instruction will be ignored if the

WPEN bit (bit 7, byte 0) of the STATUS

is asserted.

Note:

Once the Security register has been

locked, it is not possible to unlock it.

Note:

If the CS pin is deasserted before the end

of the 32-bit sequence, the sequence will

be aborted, and no write cycle will take

place.

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