25CS160-ISLASHST datasheet(28/53 Pages) MICROCHIP

28 / 53 page

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Preliminary

DS20007008B-page 28

25CS160

FIGURE 9-2:

WRITE SECURITY REGISTER (

WREX) BYTE WRITE SEQUENCE

FIGURE 9-3:

WRITE SECURITY REGISTER (

WREX) PAGE WRITE SEQUENCE

FIGURE 9-4:

LOCK SECURITY REGISTER (

LOCK) SEQUENCE

SCK

234

56 7

9 10 11 12

10 0 0 0 0

1 0

WREX Opcode (82h)

Address Bits A15-A0(2)

XX X X X 0

D7 D6 D5 D4 D3 D2 D1 D0

Data In

MSb

AA A

Note 1:

This sequence initiates a self-timed internal write cycle on the rising edge of CS after a valid sequence.

A15 through A6 are “don't care” bits, except for A10, which must be a logic ‘0’, and A5, which must be a logic ‘1’, in

order to write to the user-programmable, lockable ID page.

High-Impedance

TWC(1)

SCK

234

567

Data In Byte n (32 max.)

MSb

1 0000 0 1 0 X X X

AA A

WREX Opcode (82h)

Data In Byte 1

MSb

D7 D6 D5 D4 D3 D2 D1 D0

High-Impedance

825

Note 1:

This sequence initiates a self-timed internal write cycle on the rising edge of CS after a valid sequence.

A15 through A6 are “don't care” bits, except for A10 which must be a logic ‘0’, and A5, which must be a logic ‘1’, in

order to write to the user-programmable, lockable ID page.

Address Bits A15-A0(2)

TWC(1)

SCK

234

567

9 10 11 12

High-Impedance

1 0 0 0 00

LOCK Opcode (82h)

XX XX X 1

XX X X X X 1 X

MSb

XX X

825

Note 1:

This sequence initiates a self-timed internal write cycle on the rising edge of CS after a valid sequence.

A15 through A0 are “don't care” bits, except for A10, which must be a logic ‘1’.

Address Bits A15-A0(2)

Data In (xxxxxx1xb)

TWC(1)

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