PRELIMINARY
CYP15G0401TB
Document #: 38-02112 Rev. **
Page 8 of 30
Device Control Signals
PARCTL
Three-level Select [3],
static control input
Parity Check Control. Used to control the different parity check functions. When
LOW, parity check is disabled. When MID, and the 8B/10B Encoder is enabled
(TXMODE[1]
≠ LOW), TXDx[7:0] inputs are checked (along with TXOPx) for valid
ODD parity. When the Encoder is disabled (TXMODE[1]
= LOW), theTXDx[7:0] and
TXCTx[1:0] inputs are checked (along with TXOPx) for valid ODD parity. When HIGH,
parity check is enabled. The TXDx[7:0] and TXCTx[1:0] inputs are checked (along
with TXOPx) for valid ODD parity. See Table 2 for details.
SPDSEL
Three-level Select [3]
static control input
Serial Rate Select. This input specifies the operating bit-rate range of the transmit
PLLs. LOW = 195–400 MBd, MID = 400–800 MBd, HIGH = 800–1500 MBd. When
SPDSEL is LOW, setting TXRATE = HIGH (Half-rate Reference Clock) is invalid.
TRSTZ
LVTTL Input,
internal pull-up
Device Reset. Active LOW. Initializes all state machines and counters in the device.
When sampled LOW by the rising edge of REFCLK
↑, this input resets the internal
state machines. When the reset is removed (TRSTZ sampled HIGH by REFCLK
↑),
the status and data outputs will become deterministic in less than 16 REFCLK cycles.
The BISTLE and OELE latches are reset by TRSTZ. If the Phase-align Buffer is used,
TRSTZ should be applied after power up to initialize the internal pointers into these
memory arrays.
REFCLK
±
Differential LVPECL or
single-ended
LVTTL Input Clock
Reference Clock. This clock input is used as the timing reference for the transmit
PLL. This input clock may also be selected to clock the transmit parallel interfaces.
When driven by a single-ended LVCMOS or LVTTL clock source, connect the clock
source to either the true or complement REFCLK input, and leave the alternate
REFCLK input open (floating). When driven by an LVPECL clock source, the clock
must be a differential clock, using both inputs. When TXCKSEL = LOW, REFCLK is
also used as the clock for the parallel transmit data (input) interface.
Analog I/O and Control
OUTA1
±
OUTB1
±
OUTC1
±
OUTD1
±
CML Differential
Output
Primary Differential Serial Data Outputs. These PECL-compatible CML outputs
(+3.3V referenced) are capable of driving terminated transmission lines or standard
fiber-optic transmitter modules.
OUTA2
±
OUTB2
±
OUTC2
±
OUTD2
±
CML Differential
Output
Secondary Differential Serial Data Outputs. These PECL-compatible CML outputs
(+3.3V referenced) are capable of driving terminated transmission lines or standard
fiber-optic transmitter modules.
OELE
LVTTL Input,
asynchronous,
internal pull-up
Serial Driver Output Enable Latch Enable. Active HIGH. When OELE = HIGH, the
signals on the BOE[7:0] inputs directly control the OUTxy
± differential drivers. When
the BOE[x] input is HIGH, the associated OUTxy
± differential driver is enabled. When
the BOE[x] input is LOW, the associated OUTxy
± differential driver is powered down.
The specific mapping of BOE[7:0] signals to transmit output enables is listed in
Table 8. When OELE returns LOW, the last values present on BOE[7:0] are captured
in the internal Output Enable Latch. If the device is reset (TRSTZ is sampled LOW),
the latch is reset to disable all outputs.
BISTLE
LVTTL Input,
asynchronous,
internal pull-up
Transmit BIST Latch Enable. Active HIGH. When BISTLE = HIGH, the signals on
the BOE[7:0] inputs directly control the transmit BIST enables. When the BOE[x] input
is LOW, the associated transmit channel is configured to generate the BIST sequence.
When the BOE[x] input is HIGH, the associated transmit channel is configured for
normal data transmission. The specific mapping of BOE[7:0] signals to transmit BIST
enables is listed in Table 8. When BISTLE returns LOW, the last values present on
BOE[7:0] are captured in the internal BIST Enable Latch. When the latch is closed, if
the device is reset (TRSTZ is sampled LOW), the latch is reset to disable BIST on all
transmit channels.
Pin Descriptions (continued)
CYP15G0401TB Quad HOTLink II Transmitter
Pin Name
I/O Characteristics
Signal Description
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