PRELIMINARY
CYP15G0401TB
Document #: 38-02112 Rev. **
Page 17 of 30
tTXCLKOD+
TXCLKO+ Duty Cycle with 60% HIGH time
–1.0
+0.5
ns
tTXCLKOD–
TXCLKO– Duty Cycle with 40% HIGH time
–0.5
+1.0
ns
CYP15G0401TB REFCLK Switching Characteristics Over the Operating Range
fREF
[19]
REFCLK Clock Frequency
19.5
150
MHz
tREFCLK
REFCLK Period
6.66
51.28
ns
tREFH
REFCLK HIGH Time (TXRATE = HIGH)
5.9
ns
REFCLK HIGH Time (TXRATE = LOW)
2.9 [16]
ns
tREFL
REFCLK LOW Time (TXRATE = HIGH)
5.9
ns
REFCLK LOW Time (TXRATE = LOW)
2.9 [16]
ns
tREFD
[20]
REFCLK Duty Cycle
30
70
%
tREFR
[16, 17, 18]
REFCLK Rise Time (20% – 80%)
2
ns
tREFF
[16, 17, 18]
REFCLK Fall Time (20% – 80%)
2
ns
tTREFDS
Transmit Data Setup Time to REFCLK (TXCKSEL
= LOW)
1.7
ns
tTREFDH
Transmit Data Hold Time from REFCLK (TXCKSEL
= LOW)
0.8
ns
CYP15G0401TB Transmit Serial Outputs and TX PLL Characteristics Over the Operating Range
Parameter
Description
Condition
Min.
Max.
Unit
tB
Bit Time
5100
649
ps
tRISE
[16]
CML Output Rise Time 20% – 80% (CML Test
Load)
SPDSEL = HIGH
60
270
ps
SPDSEL = MID
100
500
ps
SPDSEL = LOW
180
1000
ps
tFALL
[16]
CML Output Fall Time 80% – 20% (CML Test
Load)
SPDSEL = HIGH
60
270
ps
SPDSEL = MID
100
500
ps
SPDSEL = LOW
180
1000
ps
tDJ
[16, 21, 23]
Deterministic Jitter (peak-peak)
IEEE 802.3z[24]
25
ps
tRJ
[16, 22, 23]
Random Jitter (
σ)
IEEE 802.3z[24]
11
ps
tTXLOCK
Transmit PLL lock to REFCLK
200
us
CYP15G0401TB AC Characteristics Over the Operating Range (continued)
Parameter
Description
Min.
Max.
Unit
Capacitance [16]
Parameter
Description
Test Conditions
Max.
Unit
CINTTL
TTL Input Capacitance
TA = 25°C, f0 = 1 MHz, VCC = 3.3V
7
pF
CINPECL
PECL input Capacitance
TA = 25°C, f0 = 1 MHz, VCC = 3.3V
4
pF
Notes:
19. While transmitting to a remote HOTLink II receiver the frequency difference between the transmitter and receiver reference clocks must be within ±1500-PPM.
While transmitting to an unknown remote receiver compliant to a particular standard, the stability of the crystal needs to be within the limits specified by the
appropriate standard. For example, to be IEEE 802.3z Gigabit Ethernet compliant, the frequency stability of the crystal needs to be within ±100 PPM.
20. The duty cycle specification is a simultaneous condition with the tREFH and tREFL parameters. This means that at faster character rates the REFCLK duty cycle
cannot be as large as 30% – 70%.
21. While sending continuous K28.5s, outputs loaded to a balanced 100
Ω load, measured at the cross point of differential outputs, over the operating range.
22. While sending continuous K28.7s, after 100,000 samples measured at the cross point of differential outputs, time referenced to REFCLK input, over the operating
range.
23. Total jitter is calculated at an assumed BER of 1E –12. Hence: total jitter (tJ) = (tRJ * 14) + tDJ.
24. Also meets all Jitter Generation requirements as specified by OBSAI RP3, CPRI, ESCON, FICON, Fibre Channel and DVB-ASI.
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