7 / 14 page

W144
Document #: 38-07153 Rev. *B
Page 7 of 14
Data Byte 2
7–
–
(Reserved)
–
–
0
6
7
PCI_F
Clock Output Disable
Low
Active
1
5
–
–
(Reserved)
–
–
0
4
13
PCI5
Clock Output Disable
Low
Active
1
3
12
PCI4
Clock Output Disable
Low
Active
1
2
11
PCI3
Clock Output Disable
Low
Active
1
1
10
PCI2
Clock Output Disable
Low
Active
1
0
8
PCI1
Clock Output Disable
Low
Active
1
Data Byte 3
7–
–
(Reserved)
–
–
0
6–
–
(Reserved)
–
–
0
5
26
48MHz
Clock Output Disable
Low
Active
1
4
25
24MHz
Clock Output Disable
Low
Active
1
3–
–
(Reserved)
–
–
0
2
21, 20,
18, 17
SDRAM8:11
Clock Output Disable
Low
Active
1
1
32, 31,
29, 28
SDRAM4:7
Clock Output Disable
Low
Active
1
0
38, 37,
35, 34
SDRAM0:3
Clock Output Disable
Low
Active
1
Data Byte 4
7–
–
(Reserved)
–
–
0
6–
–
(Reserved)
–
–
0
5–
–
(Reserved)
–
–
0
4–
–
(Reserved)
–
–
0
3–
–
(Reserved)
–
–
0
2–
–
(Reserved)
–
–
0
1–
–
(Reserved)
–
–
0
0–
–
(Reserved)
–
–
0
Data Byte 5
7–
–
(Reserved)
–
–
0
6–
–
(Reserved)
–
–
0
5–
–
(Reserved)
–
–
0
4
47
IOAPIC
Clock Output Disable
Low
Active
1
3–
–
(Reserved)
–
–
0
2–
–
(Reserved)
–
–
0
1
46
REF1
Clock Output Disable
Low
Active
1
0
2
REF0
Clock Output Disable
Low
Active
1
Data Byte 6
7–
–
(Reserved)
–
–
0
6–
–
(Reserved)
–
–
0
5–
–
(Reserved)
–
–
0
4–
–
(Reserved)
–
–
0
3–
–
(Reserved)
–
–
0