W144HT datasheet(8/14 Pages) CYPRESS

8 / 14 page

W144

Document #: 38-07153 Rev. *B

Page 8 of 14

2–

–

(Reserved)

–

1–

–

(Reserved)

–

0–

–

(Reserved)

–

Data Byte 6 (continued)

Data Byte 7

7–

–

(Reserved)

–

6–

–

(Reserved)

–

5–

–

(Reserved)

–

4–

–

(Reserved)

–

3–

–

(Reserved)

–

2–

–

(Reserved)

–

1–

–

(Reserved)

–

0–

–

(Reserved)

–

Table 6. Additional Frequency Selections through Serial Data Interface Data Bytes[2]

Input Conditions

Output Frequency

Data Byte 0, Bit 3 = 1

CPU, SDRAM Clocks

(MHz)

PCI Clocks

(MHz)

Bit 2

SEL_3

Bit 6

SEL_2

Bit 5

SEL_1

Bit 4

SEL_0

133.6

33.4 (CPU/4)

124

31 (CPU/4)

150

37.5 (CPU/4)

140

35 (CPU/4)

105

35 (CPU/3)

110

36.7 (CPU/3)

115

39.3 (CPU/3)

120

40 (CPU/3)

100.2

33.4 (CPU/3)

133

44.3 (CPU/3)

112

37.3 (CPU/3)

103

34.3 (CPU/3)

66.8

33.4 (CPU/2)

83.3

41.7 (CPU/2)

37.5 (CPU/2)

124

41.3 (CPU/3)

Table 7. Select Function for Data Byte 0, Bits 0:1

Function

Input Conditions

Output Conditions

Data Byte 0

CPU_F,

CPU1

PCI_F,

PCI1:5

REF0:1,

IOAPIC

48MHZ

24MHZ

Bit 1

Bit 0

Normal Operation

Note 1

14.318 MHz

48 MHz

24 MHz

Spread Spectrum

±0.5%

14.318 MHz

48 MHz

24 MHz

Three-state

Hi-Z

Note:

2. CPU and PCI frequency selections are listed in Table 1 and Table 6.

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