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AT25DF021A-DWFHT Datasheet(PDF) 15 Page - Renesas Technology Corp

Part # AT25DF021A-DWFHT
Description  2-Mbit, 1.65 V Minimum SPI Serial Flash Memory with Dual-I/O Support
PDF  59 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

AT25DF021A-DWFHT Datasheet(HTML) 15 Page - Renesas Technology Corp

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DS-AT25DF021A-042 Rev. L
Page 15
8/7/23
© 2023 Renesas Electronics
AT25DF021A Datasheet
7.2
Dual-Output Read Array
The Dual-Output Read Array command is similar to the standard Read Array command and can be used to
sequentially read a continuous stream of data from the device by simply providing the clock signal once the initial
starting address has been specified. Unlike the standard Read Array command, however, the Dual-Output Read
Array command allows two bits of data to be clocked out of the device on every clock cycle, rather than just one.
The Dual-Output Read Array command can be used at any clock frequency, up to the maximum specified by
fRDDO. To perform the Dual-Output Read Array operation, the CS pin must first be asserted and then the opcode
3Bh must be clocked into the device. After the opcode has been clocked in, the three address bytes must be
clocked in to specify the location of the first byte to read within the memory array. Following the three address
bytes, a single dummy byte must also be clocked into the device.
After the three address bytes and the dummy byte have been clocked in, additional clock cycles result in data
being output on both the SO and SI pins. The data is always output with the MSB of a byte first and the MSB is
always output on the SO pin. During the first clock cycle, bit seven of the first data byte is output on the SO pin,
while bit six of the same data byte is output on the SIO pin. During the next clock cycle, bits five and four of the first
data byte are output on the SO and SIO pins, respectively. The sequence continues with each byte of data being
output after every four clock cycles. When the last byte (03FFFFh) of the memory array has been read, the device
continues reading from the beginning of the array (000000h). No delays are incurred when wrapping around from
the end of the array to the beginning of the array.Deasserting the CS pin stops the read operation and put the SO
and SI pins into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full
byte of data be read.
Figure 10. Dual-Output Read Array
SI (SIO)
SO
SCK
CS
OPCODE
High-Impedance
0
0
0
1
1
1
AAAA
A
A
A
AXXXXXXXX D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
A
011
123456789 10 11 12 13
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
ADDRESS BITS A23-A0
DON’T CARE
Output
Data Byte 1
Output
Data Byte 2



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