AT25FF321A datasheet(39/112 Pages) RENESAS

39 / 112 page

DS-AT25FF321A-181 Rev. R

Page 39

2024-12-20

AT25FF321A Datasheet

Table 12 shows the operation of the SRP[1:0] volatile Status register bits during normal operation.

0SRP1

Status Register

Protect 1

R/W

The SRP1 bit works in conjunction with the SRP0 bit in Status

protection include software protection, hardware protection, one-time

programmable (OTP) protection, and reset lock-down protection. See

Table 12 for an encoding of these bits.

Table 12. Status Register During Normal Operation

SRP1

SRP0

SRLOCK

Type of Protection

Description

Software Protected

(protection is controlled by the

CMPRT, BPSIZE, TB, BP[2:0], or

WPS bits

When both the SRP0 and SRP1 bits are 0, the Status

registers can be written by executing a Write Status

WEL bit of this register. Note that the WP pin has no

meaning during this type of operation.

Hardware protected

(protection is controlled by the WP

pin)

When the SRP[1:0] bits are 0, 1 respectively, and the

WP pin is low, the registers are hardware protected and

cannot be written to.

Hardware Unprotected

(protection is controlled by the

CMPRT, BPSIZE, TB, BP[2:0], or

WPS bits

When the SRP[1:0] bits are 0, 1 respectively, and the

WP pin is high, the registers are not hardware

protected and can be written to by executing a Write

Status Register command (01h, 31h, 11h, 71h) and

setting the WEL bit of this register.

Hardware Protected

When the SRP[1:0] bits are 1, 0 respectively, the Status

registers are write protected and cannot be written until

the device is reset (caused by a power-cycle, hardware

reset, or software reset). After reset, hardware changes

the state of the SRP[1:0] bits as shown in Table 12.

Reset Lockdown

When the SRP[1:0] bits are 1,1 respectively, and the

SRLOCK bit is 0, the Status registers are write

protected and cannot be written until the device is reset

(caused by a power-cycle, hardware reset or software

reset). After reset, hardware changes the state of

SRP[1:0] bits as shown in Table 12.

OTP

When the SRP[1:0] bits are 1,1 respectively, and the

SRLOCK bit is 1, the Status registers are permanently

write protected.

Table 11. Status Register 2 Format (continued)

Bit #

Acronym

Name

Type

Default

Description

AT25FF321A Datasheet(PDF) 39 Page - Renesas Technology Corp

AT25FF321A Datasheet(HTML) 39 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL