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AT25FF321A Datasheet(PDF) 74 Page - Renesas Technology Corp

Part # AT25FF321A
Description  32-Mbit, 1.65 V - 3.6 V SPI Serial Flash Memory with Multi-I/O Support
PDF  112 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

AT25FF321A Datasheet(HTML) 74 Page - Renesas Technology Corp

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DS-AT25FF321A-181 Rev. R
Page 74
2024-12-20
© 2024 Renesas Electronics
AT25FF321A Datasheet
6.19 Read Block Lock (3Ch/3Dh)
The Read Block Lock commands allow the user to read the status of the lock bits in each block.
The individual block
locks are used to protect any individual block. The default value for all individual block lock bits is 1 upon device
power on or after reset.
The 3Ch and 3Dh commands perform the exact same operation. These two commands are identical and are
provided for backward compatibility purposes.
6.19.1
Command Prerequisites
The WPS bit in Status Register 3 must be set. When WPS is set, software uses the Block Lock (36h) and Block
Unlock (39h) commands to lock and unlock blocks of memory. If the WPS bit is cleared, write protection is
determined by the combination of CMP, SEC, TB, BP[2:0] bits in the Status Registers. The Read Block Lock
command must not be used to determine the protection status of any region of the memory. See Section 4.8.1 for
more information on the protection scheme.
6.19.2
Transfer Format
The 3Ch and 3Dh commands follow the 1-1-1 transfer format described in Section 4.2, where the command and
address are transferred on the SI pin, and data is transferred on the SO pin. Figure 7 shows a timing diagram for
this transaction.
6.19.3
Transfer Sequence
To perform the Read Block Lock operation, the CS pin is asserted and the information transferred as follows:
▪ The 3dh or 3Dh command is clocked into the device. Eight clocks are required to transfer the command. The
most significant bit of the command is transferred first.
▪ Three address bytes are clocked in to specify the starting address location of the first byte to read within the
buffer. A total of 24 clocks are required to transfer the address. The most significant bit of the address (A[23]) is
transferred first.
▪ Data is output on the SO pin and requires eight clock cycles. The MSB of the lock value is driven onto the SO
pin first, and the LSB is driven out last. If the LSB is 1, the corresponding block is locked and no erase or
program operation can be executed to that block. If the LSB is 0, the block is unlocked, indicating that
program/erase operations are allowed. The remaining bits 7:1 of this value are undefined.
If CS is kept low and additional data is clocked out, the device simply repeats the same byte over and over
again until CS goes high. Out of the 8 bits in this byte, the LSB (bit 0) has the lock bit information, the rest of the
are undefined. The lock bit information corresponds to the region of memory that encapsulates the 20-bit
address provided by the user. So for example:
- If the user provides an address of 0x000000, the device returns the lock status of the 4 kB region from
0x000000 - 0x000FFF.
- If the user provides an address of 0x001234, the device returns the lock status of the 4 kB region 0x001000
- 0x001FFF.
6.19.4
Programming Restrictions
The Read Block Lock command adheres to the following programming restrictions.
▪ The complete command must be clocked into the device before the CS pin is deasserted.



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