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AT25FF321A Datasheet(PDF) 89 Page - Renesas Technology Corp |
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AT25FF321A Datasheet(HTML) 89 Page - Renesas Technology Corp |
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89 / 112 page ![]() DS-AT25FF321A-181 Rev. R Page 89 2024-12-20 © 2024 Renesas Electronics AT25FF321A Datasheet 6.31 Ultra-Deep Power-Down (79h) The Ultra-Deep Power-Down (UDPD) mode allows the device to further reduce energy consumption compared to Deep Power-Down mode by shutting down additional internal circuitry. The UDPD mode can be entered by either executing the 79h command, or by executing the B9h command with bit 7 (PDM) of Status Register 4 cleared. When the device is in the Ultra-Deep Power-Down mode, all commands except the ABh command are ignored. Execution of the ABh command allows the device to exit from Ultra-Deep Power-Down mode. Execution of this command while in Ultra-Deep Power-Down causes the device to initialize, and then enters standby mode. 6.31.1 Transfer Format The 79h command follows the 1-0-0 transfer format described in Section 4.2, where the command is transferred on the SI pin. No address or data are transferred for this command (see Figure 3). 6.31.2 Transfer Sequence To perform the Ultra-Deep Power-Down operation, the CS pin is asserted and the information transferred as follows: ▪ The 79h command is clocked into the device. Eight clocks are required to transfer the command. The most significant bit of the command is transferred first. ▪ When the CS pin is deasserted, the device enters the Ultra-Deep Power-Down mode within the maximum time of tEUDPD. Any additional data clocked into the device after this command is ignored. Figure 29 shows a diagram with this timing parameter. Figure 29. Entering Ultra-Deep Power-Down State See Table 18 for more information on the transfer sequence for this command. 6.31.3 Programming Restrictions The following events can cause the Ultra-Deep Power-Down operation to be aborted. ▪The CS pin must be deasserted on a byte boundary (multiple of eight bits). Otherwise, the device aborts the operation and return to the standby mode once the CS pin is deasserted. Also, the device defaults to the standby mode after a power cycle. ▪ The 79h command is ignored if an internally self-timed operation such as a program or erase cycle is in progress. The 79h command must be reissued after the internally self-timed operation has been completed. Software can monitor the RDY/BSY bit in Status Register 1 to determine when the program or erase operation has completed. SCK CS SI SO MSB ICC 23 1 0 0 67 5 4 Opcode High-impedance Ultra-Deep Power-Down Mode Current Active Current Standby Mode Current t EUDPD 1111001 Mode 3 Mode 0 |
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