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M58LR128KC Datasheet(PDF) 9 Page - Numonyx B.V |
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M58LR128KC Datasheet(HTML) 9 Page - Numonyx B.V |
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9 / 108 page  M58LRxxxKC, M58LRxxxKD Description 9/108 The M58LRxxxKC/D features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. All blocks have three levels of protection. They can be locked and locked-down individually preventing any accidental programming or erasure. There is an additional hardware protection against program and erase. When VPP ≤VPPLK all blocks are protected against program or erase. All blocks are locked at power-up. The device includes 17 Protection Registers and 2 Protection Register locks, one for the first Protection Register and the other for the 16 One-Time-Programmable (OTP) Protection Registers of 128 bits each. The first Protection Register is divided into two segments: a 64 bit segment containing a unique device number written by Numonyx, and a 64 bit segment that is OTP by the user. The user programmable segment can be permanently protected. Figure 4, shows the Protection Register memory map. The devices are supplied with all the bits erased (set to ’1’) Note: The M58LRxxxKC/D is only available as part of a multichip package. |
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