M58LR128KC datasheet(21/108 Pages) NUMONYX

21 / 108 page

M58LRxxxKC, M58LRxxxKD

Command interface

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4.6

Block Erase command

The Block Erase command erases a block. It sets all the bits within the selected block to ’1,

and all previous data in the block is lost.

If the block is protected then the erase operation aborts, the data in the block does not

change, and the Status Register outputs the error.

Two bus write cycles are required to issue the command:

●

The first bus cycle sets up the Block Erase command.

●

The second latches the block address and starts the Program/Erase Controller.

If the second bus cycle is not the block erase confirm code, Status Register bits SR4 and

SR5 are set and the command is aborted.

Once the command is issued the bank enters read Status Register mode and any read

operation within the addressed bank outputs the contents of the Status Register. A Read

Array command is required to return the bank to read array mode.

During block erase operations the bank containing the block being erased only accepts the

Read Array, Read Status Register, Read Electronic Signature, Read CFI Query, and the

Program/Erase Suspend commands; all other commands are ignored.

The block erase operation aborts if Reset, RP, goes to VIL. As data integrity cannot be

guaranteed when the block erase operation is aborted, the block must be erased again.

Refer to Section 8 for detailed information about simultaneous operations allowed in banks

not being erased.

Typical Erase times are given in Table 18: Program/erase times and endurance cycles.

See Appendix C, Figure 21: Block erase flowchart and pseudocode for a suggested

flowchart for using the Block Erase command.

4.7

Blank Check command

The Blank Check command checks whether a main array block has been completely

erased. Only one block at a time can be checked. To use the Blank Check command VPP

must be equal to VPPH. If VPP is not equal to VPPH, the device ignores the command and no

error is shown in the Status Register.

Two bus cycles are required to issue the Blank Check command:

●

The first bus cycle writes the Blank Check command (BCh) to any address in the block

to be checked.

●

The second bus cycle writes the Blank Check Confirm command (CBh) to any address

in the block to be checked and starts the blank check operation.

If the second bus cycle is not Blank Check Confirm, Status Register bits SR4 and SR5 are

set to '1' and the command aborts.

Once the command is issued, the addressed bank automatically enters Status Register

mode and further reads within the bank output the Status Register contents.

The only operation permitted during blank check is read Status Register. Dual operations

are not supported while a blank check operation is in progress. Blank check operations

cannot be suspended and are not allowed while the device is in Program/Erase Suspend.

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