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M58LR128KC Datasheet(PDF) 13 Page - Numonyx B.V |
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M58LR128KC Datasheet(HTML) 13 Page - Numonyx B.V |
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13 / 108 page  M58LRxxxKC, M58LRxxxKD Signal descriptions 13/108 2 Signal descriptions See Figure 1: Logic diagram and Table 1: Signal names for a brief overview of the signals connected to this device. 2.1 Address inputs (ADQ0-ADQ15 and A16-Amax) Amax is the highest order address input. It is equal to A22 in the M58LR128KC/D and to A23 in the M58LR256KC/D. The address inputs select the cells in the memory array to access during bus read operations. During bus write operations they control the commands sent to the command interface of the Program/Erase Controller. 2.2 Data input/output (ADQ0-ADQ15) The data I/O output the data stored at the selected address during a bus read operation or input a command or the data to be programmed during a bus write operation. 2.3 Chip Enable (E) The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at VILand Reset is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level. 2.4 Output Enable (G) The Output Enable input controls data outputs during the bus read operation of the memory. 2.5 Write Enable (W) The Write Enable input controls the bus write operation of the memory’s command interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable, whichever occurs first. 2.6 Write Protect (WP) Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at VIL, the lock-down is enabled and the protection status of the locked- down blocks cannot be changed. When Write Protect is at VIH, the lock-down is disabled and the locked-down blocks can be locked or unlocked. (Refer to Table 17: Lock status). |
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