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ESP32-P4 Datasheet(PDF) 2 Page - ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. |
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ESP32-P4 Datasheet(HTML) 2 Page - ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. |
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2 / 93 page ![]() Product Overview ESP32-P4 is a high-performance MCU that supports large internal memory and has powerful image and voice processing capabilities. The MCU consists of a High Performance (HP) system and a Low Power (LP) system. The HP system contains a RISC-V dual-core CPU and rich peripherals, while the LP system contains a low-power RISC-V single-core CPU and various peripherals optimized for low-power applications. The functional block diagram of the SoC is shown below. For more information on power consumption, see Section 4.1.4.6 Low-Power Management. HP Core System Security JTAG HP Peripherals ESP32-P4 — Espressif’s High Performance MCU MCPWM GPIO UART TWAI® GP Timers I2S with PDM I2C Pulse Counter LED PWM SPI RMT DIG ADC Controller System Timer Modules having power in specific power modes: Optional in Deep-sleep Active, Light-sleep GDMA SOC ETM Bit Scrambler Brownout All modes L2ROM JPEG Codec ISP PPA 2D-DMA DW-GDMA H264 Encoder I3C Master & Slave MIPI CSI MIPI DSI LCD Interface Camera Interface Parallel IO Debug Probe Power Management Unit BAT Power Supply Low Power System WDT Option 0 in Light-sleep LP Peripherals LP Mailbox eFuse Controller ⚙ LP GPIO ⚙ Touch Sensor ⚙ GP & WDT & LP Timers & Super WDT ⚙ Option 1 in Light-sleep RISC-V 32-bit Dual-core Microprocessor 400 MHz ⚙ ⚙ ⚙ ⚙ ⚙ ⚙ ⚙ ⚙ ⚙ ⚙ ⚙ ⚙ ⚙ ⚙ ⚙ ⚙ ⚙ ⚙ ⚙ ⚙ ⚙ ⚙ ⚙ ⚙ ⚙ ⚙ ⚙ ⚙ ⚙ ⚙ ⚙ ⚙ ⚙ ⚙ ⚙ HPSPM L2MEM SD/MMC Host ⚙ USB Serial JTAG USB 2.0 OTG High-speed ⚙ USB 2.0 OTG Full-speed ⚙ Ethernet ⚙ LP Core System LPSPM LPROM ⚙ RISC-V 32-bit Single-core Microprocessor 40 MHz ⚙ JTAG ⚙ SHA ⚙ HMAC ⚙ TEE ⚙ Digital Signature ⚙ XTS_AES ⚙ RSA_DS ⚙ TRNG ⚙ APM ⚙ ECC ⚙ ECDSA_DS ⚙ AES ⚙ Secure Boot ⚙ 4096-bit OTP ⚙ PMP and PMA ⚙ -7.5 像素 2-level Cache ⚙ ⚙ ⚙ ⚙ LP UART ⚙ Temperature Sensor ⚙ ⚙ LP DIG ADC Controller ⚙ LP SPI ⚙ LP I2S ⚙ LP I2C ⚙ HUK and Key Manager ⚙ ESP32-P4 Functional Block Diagram |
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